AS1156/AS1154
Data Sheet - Applications
Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length.
Keep the LVDS and any other digital signals separated from each other to reduce crosstalk.
Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals.
Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent
coupling.
Separate the input LVDS signals from the output signals planes with the power and ground planes for best results.
Figure 20. Driver Propagation Delay and Transition Time Waveforms
1.5V
1.5V
INx
tPLHD
tPHLD
VOH
VOL
OUTx-
0 Differential
0
OUTx+
80%
0
80%
VDIFF = (VOUTx+) - (VOUTx-)
00
20%
20%
tTLH
tTHL
Figure 21. Driver Propagation Delay and Transition Time Test Circuit
OUTx+
Generator
RL
CL
50Ω
OUTx-
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