AS1112
Datasheet ꢀ Detailed Description
Figure 12. Dot Correction Data Input Timing Diagram
Dot Correction Mode
Data Input Cycle n
Dot Correction Mode
Data Input Cycle n +1
VCC
GND
MODE
SDI
DCn-1
LSB
DCn
DCn
DCn
DCn
DCn
DCn+1
DCn+1
MSB
MSB-1
MSB-2
LSB+1
LSB
MSB
MSB-1
tSU0
tWH0
2
CLK
1
1
95
96
1
2
tWL0
DCn-1
MSB
DCn-1
MSB-1
DCn-1
MSB-2
DCn-1
LSB+1
DCn-1
LSB
DCn
DCn
MSB-1 MSB-2
DCn
MSB
tWH2
SDO
LD
tSU1
tH1
Setting Greyscale Brightness
The brightness of each channel output can be adjusted using a 12 bitsꢀperꢀchannel PWM control scheme which results in 4096 brightness steps,
from 0% to 100% brightness. The brightness level for each output is calculated as:
GSn
%Brightness =
x 100
(EQ 4)
4095
Where:
GSn is the programmed greyscale value for OUTn (GSn = 0 to 4095);
n = 0 to 15 greyscale data for all outputs.
The device powers up with the following default seetings: GS = 4095 and DC = 63.
The input shift register shifts greyscale data into the greyscale register for all channels simultaneously. The complete greyscale data format conꢀ
sists of 16 x 12 bit words, which forms a 192ꢀbit wide data packet (see Figure 13).
Note: The data packet must be clocked in with the MSB first.
Figure 13. Greyscale Data Packet Format
MSB
191
LSB
0
180
179
12
11
...
...
...
GS15.11
GS15.0 GS14.11
GS1.0
GS0.11
GS0.0
GS OUT15
GS OUT14:GS OUT1
GS OUT0
When pin MODE is tied to GND, the AS1112 enters greyscale data input mode. The device switches the input shift register to 192ꢀbit width. After
all data is clocked in, the rising edge of the LD signal latches the data into the greyscale register (see Figure 14).
All greyscale data in the input shift register is replaced with status information data (SID) after latching into the greyscale register.
www.austriamicrosystems.com/LEDꢀDriverꢀICs/AS1112
Revision 1.13
12 ꢀ 19
AMSCO [ AMS(艾迈斯) ]
