Data Sheet AS1100
Decode-Mode Register
In the AS1100 a BCD decoder is included. Every digit can
be selected via register 09h to be decoded. The BCD code
consists of the numbers 0-9, E,H, L,P and -. In register 09h
a logic high enables the decoder for the appropriate digit. In
case that the decoder is bypassed (logic low) the data Bits
D7-D0 correspond to the segment lines of the AS1100. In
table 4 some possible settings for register 09h are shown.
Bit D7, which corresponds to the decimal point, is not
affected by the settings of the decoder. Logic high means
that the decimal point is displayed. In table 5 the font of the
Code B decoder is shown. In table 6 the correspondence of
the register to the appropriate segments of a 7 segment
display is shown (see figure 2)
Intensity Control and Interdigit Blanking
Brightness of the display can be controlled in an analog way
by changing the external resistor (R
SET
). The current, which
flows between VDD and I
SET
, defines the current that flows
through the LEDs. The LED current is 100 times the I
SET
current. The minimum value of R
SET
should be 9.53kΩ,
which corresponds to 40mA segment current. The
brightness of the display can also be controlled digitally via
register 0Ah. The brightness can be programmed in 16
steps and is shown in table 7. An internal pulse width
modulator controls the intensity of the display.
Scan-Limit Register
The scan limit register 0Bh selects the number of digits
displayed. When all 8 digits are displayed the update
frequency is typically 800Hz. If the number of digits
displayed is reduced, the update frequency is reduced as
well. The frequency can be calculated using 8fOSC/N,
where N is the number of digits. Since the number of
displayed digits influences the brightness, the resistor R
SET
should be adjusted accordingly. Table 9 shows the
maximum allowed current, when fewer than 4 digits are
used. To avoid differences in brightness the scan limit
register should not be used to blank portions of the display
(leading zeros).
Address
D15–D12 D11 D10
X
0
0
X
0
0
X
0
0
X
0
0
X
0
1
X
0
1
X
0
1
X
0
1
X
1
0
X
X
X
X
X
X
X
1
1
1
1
1
1
1
0
0
0
1
1
1
1
Hex
Code
0xX0
0xX1
0xX2
0xX3
0xX4
0xX5
0xX6
0xX7
0xX8
0xX9
0xXA
0xXB
0xXC
0xXD
0xXE
0xXF
Register
No-Op
Digit 0
Digit 1
Digit 2
Digit 3
Digit 4
Digit 5
Digit 6
Digit 7
Decode
Mode
Intensity
Scan Limit
Shutdown
Not used
Reset and
ext. Clock
Display
Test
D9
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 2: Register address map
Mode
Shutdown
Mode
Normal
Operation
Address Code
Register Data
D7 D6 D5 D4 D3 D2 D1 D0
(Hex)
0xXC
0xXC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
Table 3: Shutdown register format (address (hex) = 0xXC)
Revision 1.32, Oct. 2004
Page 5 of 12
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