Data Sheet AS1100
Parameter
Conditions
Min
-1
Typ
Max
Symbol
Units
µA
Input Current DIN, CLK, LOAD IIH, IIL VIN = 0V or VDD
1
Logic High Input Voltage
Logic Low Input Voltage
Output High Voltage
Output Low Voltage
Hysteresis Voltage
VIH
3.5
V
V
V
V
V
VIL
0.8
0.4
VOH DOUT, ISOURCE = -1mA
VDD - 1
VOL
VI
DOUT, ISINK = 1.6mA
DIN, CLK, LOAD
1
Timing Characteristics
CLK Clock Period
tCP
tCH
tCL
100
50
ns
ns
ns
CLK Pulse Width High
CLK Pulse Width Low
CLK Rise to LOAD Rise Hold
Time
50
tCSH
0
ns
DIN Setup Time
tDS
tDH
tDO
25
0
ns
ns
ns
DIN Hold Time
Output Data Propagation Delay
LOAD Rising Edge to Next
Clock Rising Edge
CLOAD = 50pF
25
tLDCK
50
50
ns
Minimum LOAD Pulse High
Data-to-Segment Delay
tCSW
ns
tDSPD
2.25
ms
Pin Description
Pin
Name
Function
1
DIN
Data input. Data is programmed into the 16Bit shift register on the rising CLK edge
8 digit driver lines that sink the current from the common cathode of the display.
In shutdown mode the AS1100 switches the outputs to VDD
both GND pins must be connected
2, 3, 5–8, 10,
DIG 0–DIG 7
GND
11
4, 9
Strobe input. With the rising edge of the LOAD signal the 16 bit of serial data is latched into
the register.
12
LOAD
Clock input. The interface is capable to support clock frequencies up to 10MHz. The serial
data is clocked into the internal shift register with the rising edge of the CLK signal. On the
DOUT pin the data is applied with the falling edge of CLK.
Seven segment driver lines including the decimal point. When a segment is turned off the
output is connected to GND.
13
CLK
SEG A–G,
DP
14–17, 20–23
The current into ISET determines the peak current through the segments and therefore the
brightness.
18
19
24
ISET
VDD
Positive Supply Voltage (+5V)
Serial data output for cascading drivers. The output is valid after 16.5 clock cycles. The
output is never set to high impedance.
DOUT
Revision 1.32, Oct. 2004
Page 3 of 12
AMSCO [ AMS(艾迈斯) ]
