AS3525-A/-B C22O22
Data Sheet, Confidential
Table 2 Soldering Conditions
Symbol
Parameter
Min
Max
Unit
Note
260
°C
Norm IPC/JEDEC J-STD-020C, reflects
moisture sensitivity level only
Tbody
Tpeak
Dwell
Package Body Temperature
Solder Profile*
235
30
245
45
°C
s
above 217 °C
* austriamicrosystems AG strongly recommends to use underfill.
6.2 Operating Conditions
6.2.1 Supply Voltages
Table 3 Operating conditions for supply input voltages
Symbol
VB1V
Parameter
Min
Max
Unit
Note
DCDC Supply Voltage
1.0
3.6
V
BVDD
VBUS
CHGIN
Battery Supply Voltage
USB VBUS Voltage
3.2
4.0
4.5
-0.1
5.5
5.5
5.5
0.1
V
V
V
V
Charger Supply Voltage
Difference of Negative
Supplies
To achieve good performance, the
negative supply terminals should be
connected to low impedance ground
plane.
VSS3, VSS1, VSS15, BVSS,
BVSS2, AVSS, DVSS, VSSCP
6.2.2 Internal Supply Voltages
Following supply voltages for the digital system are generated by the integrated power management
Table 4 Operating conditions for internal internal supply voltages
Symbol
VDDperi
Parameter
Min
Max
Unit
Note
3.0
3.6
V
digital periphery supply voltage
to be connected to IOVDD
VDDmem
1.7
3.6
V
V
V
V
digital IO supply for MPMC PADs
to be connected to PVDD
digital core supply voltage
to be connected to CVDD; see Note (1)
USB analog supply transmit block
to be connected to UVDD
USB analog supply common block
to be connected to UVDD
VDDcore
1.08
3.15
3.15
1.26
3.45
3.45
USBVDDA33T
USBVDDA33C
DVDD
AVDD
Digital Supply Voltage
2.8
2.8
3.6
3.6
0.1
V
V
V
Digital Audio Supply Voltage (LDO2)
Analogue Supply Voltage
Analog Audio Supply Voltage (LDO1)
Difference of Negative
Supplies
vss_peri, vss_core, vss_mem,
usb_vssa33c, usb_vssa33t
-0.1
To achieve good performance, the
negative supply terminals should be
connected to low impedance ground
plane.
Note(s)
(1) For the VDD_CORE supply, voltage scaling should be applied to optimize power consumption
and CPU speed performance. For normal operation with fclk (CPU ARM-922T clock) frequencies
below 200 MHz, CVDD (supply of VDD_CORE) can be set to a lower value of 1.10 V. Only for setting
fclk of the CPU to clock frequencies above 200 MHz, the VDD_CORE supply voltage must be set to
1.20 V typical conditions.
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