AMS73CAG01808RA
-H7 (DDR3-1066)
-I9 (DDR3-1333)
Parameter
Symbol
Min
Max
Min
Max
Unit
Note
DQS, DQS delay after write leveling
mode is pro-grammed
-
-
3
tWLDQSEN
25
25
nCK
Write leveling setup time from rising CK,
CK crossing to rising DQS, DQS crossing
-
-
-
-
tWLS
tWLH
245
245
195
195
ps
ps
Write leveling hold time from rising DQS,
DQS crossing to rising CK, CK crossing
Write leveling output delay
Write leveling output error
Absolute clock period
tWLO
tWLOE
0
0
9
2
0
0
9
2
ns
ns
tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max +
tJIT(per)min
tCK(abs)
ps
tJIT(per)max
tJIT(per)min
tJIT(per)max
30
31
Absolute clock high pulse width
Absolute clock low pulse width
Clock period jitter
t
CH(abs)
0.43
-
-
0.43
-
-
tCK(avg)
tCK(avg)
ps
tCL(abs)
tJIT(per)
0.43
0.43
-90
90
-80
80
Clock period jitter during DLL locking
period
t
JIT(per,lck)
-80
80
-70
70
ps
ps
ps
Cycle to cycle period jitter
tJIT(cc)
-
-
180
160
-
-
160
140
Cycle to cycle period jitter during DLL
locking period
t
JIT(cc,lck)
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
t
ERR(2per)
-132
-157
-175
-188
-200
-209
-217
-224
-231
-237
-242
132
157
175
188
200
209
217
224
231
237
242
-118
-140
-155
-168
-177
-186
-193
-200
-205
-210
-215
118
140
155
168
177
186
193
200
205
210
215
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
Cumulative error across
n = 13,14,...49,50 cycles
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
ERR(nper)max = (1 + 0.68ln(n))*tJIT(per)max
32
t
ERR(nper)
ps
t
AMS73CAG01808RA Rev. 1.0 December 2010
27
AMS [ Advanced Monolithic Systems Ltd ]
