AMS73CAG01808RA
Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, RTT_WR impedance and
CAS write latency (CWL). The Mode Register 2 is written by asserting low on CS, RAS, CAS, WE, high on
BA1, low on BA0 and BA2, while controlling the states of address pins according to the table below.
13
A
A
12
BA
2
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Field
BA
1
1
0*1
SRT ASR
Rtt_WR
CWL
PASR*2
0*1
0*1
Mode Register 2
0
A2 A1 A0
Partial Array Self Refresh (Optional)
Full Array
A7
Self-refresh temperature range (SRT)
Normal operating temperature range
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
HalfArray (BA[2:0]=000,001,010, &011)
Quarter Array (BA[2:0]=000, & 001)
1/8th Array (BA[2:0] = 000)
Extend temperature self-refresh (Optional)
A6
3/4 Array (BA[2:0] = 010,011,100,101,110, & 111)
HalfArray (BA[2:0] = 100, 101, 110, &111)
Quarter Array (BA[2:0]=110, &111)
1/8th Array (BA[2:0]=111)
Auto Self-refresh (ASR)
Manual SR Reference (SRT)
ASR enable (Optional)
0
1
Rtt_WR*2
A10 A9
Dynamic ODT off
(Write does not affect Rtt value)
0
0
A5 A4 A3
CAS write Latency (CWL)
0
1
1
1
0
1
RZQ/4
RZQ/2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5 (tCK(avg) ≥2.5ns)
6 (2.5ns >tCK(avg) ≥1.875ns)
7 (1.875ns>tCK(avg) ≥1.5ns)
8 (1.5ns>tCK(avg) ≥1.25ns)
Reserved
Reserved
BA1
0
BA0
MRS mode
MR0
Reserved
0
1
0
1
Reserved
0
MR1
Reserved
1
MR2
1
MR3
* 1 : BA2, A8, A11 ~ A13 are RFU and must be programmed to 0 during MRS.
* 2 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled.
During write leveling, Dynamic ODT is not available.
AMS73CAG01808RA Rev. 1.0 December 2010
9
AMS [ Advanced Monolithic Systems Ltd ]
