AMS73CAG01808RA
AC Characteristics
( VDD = 1.5V±0.075V; VDDQ =1.5V±0.075V )
-H7 (DDR3-1066)
-I9 (DDR3-1333)
Parameter
Symbol
Min
Max
Min
Max
Unit
Note
Average clock cycle time
tCK(avg)
See Speed Bins Table
ns
Minimum clock cycle time
(DLL-off mode)
tCK
(DLL-off)
6
8
-
8
-
ns
Average CK high level width
Average CK low level width
tCH(avg)
tCL(avg)
0.47
0.47
7.5
0.53
0.47
0.47
6
0.53
tCK(avg)
tCK(avg)
ns
0.53
0.53
Active Bank A to Active Bank B
command period
-
-
-
-
-
-
tRRD
4
4
nCK
Four activate window
tFAW
37.5
30
ns
Address and Control input hold time
(VIH/VIL (DC100) levels)
tIH(base)
DC100
16
16
200
125
-
-
-
-
-
-
-
140
65
-
-
-
-
-
-
-
ps
ps
ps
ps
ps
ps
ps
Address and Control input setup time
(VIH/VIL (AC175) levels)
tIS(base)
AC175
Address and Control input setup time
(VIH/VIL (AC150) levels)
tIS(base)
AC150
16,24
17
125+150
100
65+125
65
DQ and DM input hold time
(VIH/VIL (DC) levels)
t
DH(base)
DQ and DM input setup time
(VIH/VIL (AC) levels)
17
t
DS(base)
tIPW
25
30
Control and Address Input pulse width
for each input
25
780
620
400
DQ and DM Input pulse width
for each input
25
tDIPW
490
13,14
13,14
DQ high impedance time
DQ low impedance time
tHZ(DQ)
tLZ(DQ)
-
300
300
-
250
250
ps
ps
-600
-500
DQS, DQS high impedance time
(RL + BL/2 reference)
13,14
13,14
12,13
t
HZ(DQS)
-
-600
-
300
300
150
-
-500
-
250
250
125
ps
ps
ps
DQS, DQS low impedance time
(RL - 1 reference)
t
LZ(DQS)
DQS, DQS to DQ Skew,
per group, per access
tDQSQ
CAS to CAS command delay
tCCD
tQH
4
-
-
4
-
-
nCK
12,13
12,13
DQ output hold time from DQS, DQS
0.38
0.38
tCK(avg)
DQS, DQS rising edge output
access time from rising CK, CK
tDQSCK
tDQSS
tDSH
-300
-0.25
0.2
300
0.25
-
-255
-0.25
0.2
255
0.25
-
ps
DQS latching rising transitions
to associated clock edges
tCK(avg)
tCK(avg)
DQS falling edge hold time
from rising CK
29
DQS falling edge setup time
to rising CK
29
tDSS
0.2
-
0.2
-
tCK(avg)
tCK(avg)
27,28
DQS input high pulse width
tDQSH
0.45
0.55
0.45
0.55
AMS73CAG01808RA Rev. 1.0 December 2010
24
AMS [ Advanced Monolithic Systems Ltd ]
