AMS73CAG01808RA
IDD Specification
( VDD = 1.5V±0.075V; VDDQ =1.5V±0.075V )
Conditions
Symbol - H7
- I9
Unit
Operating One Bank Active-Precharge Current; CKE: High; External clock: On; tCK, nRC, nRAS,
CL: see timing used table; BL: 8; AL: 0; CS: High between ACT and PRE; Command, Address: partially
toggling; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time;
Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
IDD0
IDD1
mA
85
100
13
95
Operating One Bank Active-Read-Precharge Current; CKE: High; External clock: On; tCK, nRC,
nRAS, nRCD, CL: see timing used table; BL: 81; AL: 0; CS: High between ACT, RD and PRE; Com-
mand, Address, Data IO: partially toggling; DM:stable at 0; Bank Activity: Cycling with one bank active
at a time; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
110
14
40
60
60
55
mA
mA
mA
mA
mA
mA
Precharge Power-Down Current Slow Exit; CKE: Low; External clock: On; tCK, CL: see timing used
table; BL: 8; AL: 0; CS: stable at 1; Command, Address: stable at 0; Data IO: FLOATING; DM: stable
at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal:
stable at 0; Pre-charge Power Down Mode: Slow Exit
IDD2P0
IDD2P1
IDD2N
IDD2NT
Precharge Power-Down Current Fast Exit; CKE: Low; External clock: On; tCK, CL: see timing used
table; BL: 8; AL: 0; CS: stable at 1; Command, Address: stable at 0; Data IO: FLOATING; DM:stable
at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal:
stable at 0; Pre-charge Power Down Mode: Fast Exit
35
Precharge Standby Current; CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; CS: stable at 1; Command, Address: partially toggling; Data IO: FLOATING; DM:stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable
at 0
55
Precharge Standby ODT Current; CKE: High; External clock: On; tCK, CL: see timing used table; BL:
8; AL: 0; CS: stable at 1; Command, Address: partially toggling; Data IO: FLOATING; DM:stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: tog-
gling
55
Precharge Quiet Standby Current; CKE: High; External clock: On; tCK, CL: see timing used table;
BL: 8; AL: 0; CS: stable at 1; Command, Address: stable at 0; Data IO: FLOATING; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable
at 0
IDD2Q
IDD3P
50
Active Power-Down Current; CKE: Low; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; CS: stable at 1; Command, Address: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank
Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
mA
mA
35
60
40
65
Active Standby Current; CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8; AL:
0; CS: stable at 1; Command, Address: partially toggling; Data IO: FLOATING; DM: stable at 0; Bank IDD3N
Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
Operating Burst Read Current; CKE: High; External clock: On; tCK, CL: see timing used table; BL:
8; AL: 0; CS: High between RD; Command, Address: par-tially toggling; Data IO: seamless read data
burst with different data between one burst and the next one; DM: stable at 0; Bank Activity: all banks IDD4R
open, RD commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode
Registers; ODT Signal: stable at 0
mA
mA
160
170
200
210
Operating Burst Write Current; CKE: High; External clock: On; tCK, CL: see timing used table; BL:
8; AL: 0; CS: High between WR; Command, Address: par-tially toggling; Data IO: seamless write data
burst with different data between one burst and the next one; DM: stable at 0; Bank Activity: all banks IDD4W
open, WR commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode
Registers; ODT Signal: stable at HIGH
AMS73CAG01808RA Rev. 1.0 December 2010
20