AMS73CAG01808RA
CKE Truth Table
(a) Note 1~7 apply to the entire Command truth table
(b) CKE low is allowed only if tMRD and tMOD are satisfied
CKE
3
Command (N)
2
1
1
Action (N)3
Notes
Current State
Previous Cycle
(N-1)
Current Cycle
(N)
RAS, CAS, WE, CS
L
L
L
H
L
H
L
L
L
L
L
L
L
X
Maintain Power-Down
Power Down Exit
14, 15
11, 14
Power Down
Self Refresh
DESELECT or NOP
X
L
Maintain Self Refresh
Self Refresh Exit
15, 16
L
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
REFRESH
8, 12, 16
11, 13, 14
11, 13, 14, 17
11, 13, 14, 17
11, 13, 14, 17
11
Bank(s) Active
Reading
H
H
H
H
H
H
H
Active Power Down Entry
Power Down Entry
Writing
Power Down Entry
Precharging
Refreshing
Power Down Entry
Precharge Power Down Entry
Precharge Power Down Entry
Self Refresh Entry
11,13, 14, 18
9, 13, 18
10
All Banks Idle
For more details with all signals See “Command Truth Table,” on previous page
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.
2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not included here
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh
6. CKE must be registered with the same value on tCKEmin consecutive positive clock edges. CKE must remain at the valid input level the entire time it
takes to achieve the tCKEmin clocks of registeration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period
of tIS + tCKEmin + tIH.
7. DESELECT and NOP are defined in the Command truth table
8. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period. Read or ODT commands
may be issued only after tXSDLL is satisfied.
9. Self Refresh mode can only be entered from the All Banks Idle state.
10. Must be a legal command as defined in the Command Truth Table.
11. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
12. Valid commands for Self Refresh Exit are NOP and DESELECT only.
13. Self Refresh can not be entered while Read or Write operations. See ‘Self-Refresh Operation” and ‘Power-Down Modes” on
detailed list of restrictions.
later section for a
14. The Power Down does not perform any refresh operations.
15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. It also applies to Address pins
16. VREF (Both VREFDQ and VREFCA) must be maintained during Self Refresh operation.
17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power Down is entered, otherwise Active Power
Down is entered
18. ‘Idle state’ means that all banks are closed(tRP,tDAL,etc. satisfied) and CKE is high and all timings from previous operations are satisfied
(tMRD,tMOD,tRFC,tZQinit,tZQoper,tZQCS,etc)as well as all SRF exit and Power Down exit parameters are satisfied (tXS,tXP,tXPDLL,etc)
AMS73CAG01808RA Rev. 1.0 December 2010
12
AMS [ Advanced Monolithic Systems Ltd ]
