AMS73CAG01808RA
Command Truth Table
(a) Note 1,2,3,4 apply to the entire Command truth table
(b) Note 5 applies to all Read/Write commands.
[BA=Bank Address, RA=Row Address, CA=Column Address, BC=Burst Chop, X=Don’t care, V=Valid]
CKE
BA0 A13 A12 A10
A0
-
Function
Abbreviation
CS RAS CAS WE
-
-
/
/
Notes
Previous
Current
BA2 A15
BC
AP
A9,A11
Cycle
Cycle
Mode Register Set
Refresh
Self Refresh Entry
MRS
REF
SRE
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
V
H
L
L
L
H
H
H
L
L
L
V
H
H
H
H
L
L
H
H
V
H
L
L
H
L
BA
V
V
X
V
BA
V
BA
BA
BA
BA
OP Code
V
V
X
V
V
V
V
V
X
V
V
V
V
V
X
V
L
V
V
X
V
V
V
7,9,12
Self Refresh Exit
SRX
L
H
7,8,9,12
Single Bank Precharge
Precharge all Banks
Bank Activate
Write (Fixed BL8 or BL4)
Write (BL4, on the Fly)
Write (BL8, on the Fly)
Write with Auto Precharge
(Fixed BL8 or BL4)
Write with Auto Precharge
(BL4, on the Fly)
Write with Auto Precharge
(BL8, on the Fly)
PRE
PREA
ACT
WR
WRS4
WRS8
H
H
H
H
H
H
H
H
H
H
H
H
H
Row Address (RA)
RFU
RFU
RFU
V
L
H
L
L
L
CA
CA
CA
L
L
L
L
WRA
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
L
L
L
BA
BA
BA
RFU
RFU
RFU
V
L
H
H
H
CA
CA
CA
WRAS4
WRAS8
H
Read (Fixed BL8 or BL4)
Read (BL4, on the Fly)
Read (BL8, on the Fly)
Read with Auto Precharge
(Fixed BL8 or BL4)
Read with Auto Precharge
(BL4, on the Fly)
Read with Auto Precharge
(BL8, on the Fly)
RD
RDS4
RDS8
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
BA
BA
BA
RFU
RFU
RFU
V
L
H
L
L
L
CA
CA
CA
RDA
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
BA
BA
BA
RFU
RFU
RFU
V
L
H
H
H
CA
CA
CA
RDAS4
RDAS8
H
No Operation
Device Deselected
ZQ calibration Long
ZQ calibration Short
NOP
DES
ZQCL
ZQCS
H
H
H
H
H
H
H
H
L
H
L
L
L
H
L
H
H
X
H
H
H
V
H
X
H
X
H
H
H
X
H
X
H
X
L
V
X
X
X
V
X
V
X
V
X
X
X
V
X
V
X
V
X
X
X
V
X
V
X
V
X
H
L
V
X
V
X
V
X
X
X
V
X
V
X
10
11
L
H
X
H
X
Power Down Entry
PDE
PDX
H
L
L
6,12
6,12
Power Down Exit
Note :
H
1. All DDR3 SDRAM commands are defined by states of CS, RAS, CAS, WE and CKE at the rising edge of the clock. The MSB of BA, RA, and CA are
device density and configuration dependant
2. RESET is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function.
3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register
4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”
5. Burst reads or writes cannot be terminated or interrupted and Fixed/on the fly BL will be defined by MRS
6. The Power Down Mode does not perform any refresh operations.
7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
8. Self refresh exit is asynchronous.
9. VREF(Both VREFDQ and VREFCA) must be maintained during Self Refresh operation.
10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or a wait state. The purpose of the No Operation
command (NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A No Operation command will not
terminate a previous operation that is still executing, such as a burst read or write cycle.
11. The Deselect command performs the same function as a No Operation command.
12. Refer to the CKE Truth Table for more detail with CKE transition
AMS73CAG01808RA Rev. 1.0 December 2010
11
AMS [ Advanced Monolithic Systems Ltd ]
