LP62S1664C Series
Timing Waveforms
Read Cycle 1(1, 2, 4)
tRC
Address
tAA
tOH
tOH
DOUT
Read Cycle 2(1, 2, 3)
tRC
Address
tAA
CE
tACE
5
tCHZ
5
tCLZ
tBE
HB, LB
5
5
tBLZ
tBHZ
OE
5
tOE
tOHZ
5
tOLZ
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL.
3. Address valid prior to or coincident with CE and (HB and, or LB ) transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
(February, 2002, Version 0.0)
7
AMIC Technology, Inc.