LP62S16256E-T Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
tWC
Address
tAW
tCW
CE
3
tWR
1
2
tAS
tBW
HB, LB
tWP
WE
tDH
tDW
DATA IN
4
tWHZ
tOW
DATA OUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and (HB and , or LB ).
3. tWR is measured from the earliest of CE or WE or (HB and , or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(January, 2002, Version 2.0)
11
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
