LP62S16128B-I Series
128K X 16 BIT LOW VOLTAGE CMOS SRAM
Features
n Operating voltage: 2.7V to 3.6V
n Access times: 55/70 ns (max.)
n Current:
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
Very low power version: Operating: 55ns 40mA (max.) n Data retention voltage: 2V (min.)
70ns 35mA (max.) n Available in 44-pin TSOP and 48-ball CSP (6 x 8 mm)
packages
Standby:
10mA (max.)
General Description
The LP62S16128B-I is a low operating current 2,097,152-
bit static random access memory organized as 131,072
words by 16 bits and operates on low power voltage from
2.7V to 3.6V. It is built using AMIC's high performance
CMOS process.
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configurations
n TSOP
n CSP (Chip Size Package)
48-pin Top View
A4
A3
A2
A1
A0
CE
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
2
A6
1
2
3
4
5
6
3
A7
4
OE
A
B
C
D
E
F
LB
OE
A0
A1
A2
NC
5
HB
6
LB
I/O
9
HB
A3
A5
A4
A6
I/O
I/O
1
CE
I/O1
I/O2
I/O3
I/O4
7
I/O16
I/O15
I/O14
I/O13
GND
VCC
I/O12
I/O11
I/O10
8
I/O10
I/O11
I/O
I/O
I/O
I/O
2
3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VCC
GND
GND I/O12
NC
NC
A14
A12
A9
A7
4
5
6
VCC
GND
VCC
I/O15
I/O16
NC
I/O13
I/O14
NC
A16
A15
A13
A10
I/O5
I/O6
I/O7
I/O8
I/O
I/O
7
8
I/O
9
G
H
WE
A11
WE
A16
A15
A14
A13
A12
NC
A8
A8
NC
A9
A10
A11
NC
(August, 2001, Version 1.0)
1
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
