LP621024D-I Series
Preliminary
128K X 8 BIT CMOS SRAM
Features
General Description
n Single +5V power supply
n Access times: 55/70 ns (max.)
n Current:
The LP621024D-I is a low operating current 1,048,576-bit
static random access memory organized as 131,072
words by 8 bits and operates on a single 5V power
supply.
Very low power version: Operating: 70mA (max.)
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Standby:
50mA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Output enable and two chip enable inputs for easy
application
Data retention is guaranteed at a power supply voltage
as low as 2V.
n Data retention voltage: 2V (min.)
n Available in 32-pin DIP, SOP TSOP and TSSOP
(8 X 13.4mm) packages
Product Family
Power Dissipation
Package
Operating
Temperature
VCC
Range
Product Family
Speed
Data Retention
(ICCDR, Typ.)
Standby
Operating
(ICC2, Typ.)
Type
(ISB1, Typ.)
32L DIP/
SOP/TSOP/
TSSOP
LP62S1024D
4.5V~5.5V 55ns / 70ns
10mA
-40°C ~ +85°C
0.5mA
2mA
1. Typical values are measured at VCC = 5.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
Pin Configurations
n DIP
n SOP
n TSOP/(TSSOP)
1
VCC
A15
CE2
WE
A13
A8
1
VCC
A15
CE2
WE
A13
A8
32
31
30
29
28
27
26
32
31
30
29
28
27
26
NC
A16
A14
NC
A16
A14
16
1
2
3
4
5
6
2
3
4
5
6
A12
A7
A12
A7
A6
A6
A5
A4
A3
A5
A4
A3
A9
A9
7
8
7
8
A11
OE
A11
OE
25
24
23
22
25
24
23
22
9
9
A10
A10
10
11
10
11
A2
A1
A2
A1
CE1
CE1
A0
I/O8
A0
I/O8
12
13
14
15
16
21
20
19
18
17
12
13
14
15
16
21
20
19
18
17
I/O1
I/O1
I/O7
I/O6
I/O5
I/O4
I/O7
I/O6
I/O5
I/O4
I/O2
I/O3
I/O2
I/O3
32
17
GND
GND
Pin No.
1
2
3
4
5
6
7
8
9
10
A16
26
11
12
A12
28
13
A7
14
A6
15
A5
16
A4
32
Pin
Name
A11
17
A9
18
A2
A8
19
A1
A13
20
WE
21
CE2
22
A15
VCC
24
NC
25
A14
27
Pin No.
23
29
30
31
Pin
Name
I/O3
I/O8
A3
A0
I/O1
I/O2
GND
I/O4
I/O5
I/O6
I/O7
CE1
A10
OE
PRELIMINARY (August, 2002, Version 0.0)
2
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
