LP61L1024
AC Test Conditions
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
3 ns
1.5V
See Figures 1 and 2
+3.3V
+3.3V
320W
320W
I/O
I/O
30pF*
5pF*
350W
350W
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = 0°C to 70°C)
Symbol
Parameter
Min.
Max.
Unit
Conditions
CE1 ³ VCC - 0.2V
CE2 ³ VCC - 0.2V or
CE2 £ 0.2V
VDR1
2
3.6
V
VCC for Data Retention
CE2 £ 0.2V
VDR2
2
3.6
5
V
CE1 ³ VCC - 0.2V or
CE1 £ 0.2V
VCC = 3.0V
CE1 ³ VCC - 0.2V
CE2 ³ VCC - 0.2V
VIN ³ VCC - 0.2V or
VIN £ 0.2V
ICCDR1
mA
-
-
Data Retention Current
VCC = 3.0V
CE2 £ 0.2V
ICCDR2
5
mA
CE1 £ 0.2V
VIN ³ VCC - 0.2V or
VIN £ 0.2V
tCDR
tR
Chip Disable to Data Retention Time
Operation Recovery Time
0
5
-
-
ns
See Retention Waveform
ms
(August, 2002, Version 2.1)
10
AMIC Technology, Inc.