A43L2616B
Read & Write Cycle at Different Bank @Burst Length=4
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CLOCK
CKE
High
CS
RAS
CAS
RAa
CAa
RDb
CDb
RBc
CBc
ADDR
BA0
BA1
A10/AP
RAa
RDb
RBC
tCDL
*Note 1
WE
DQM
DQ
(CL=2)
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1 QBc2
QBc0 QBc1
DQ
(CL=3)
QAa0 QAa1 QAa2 QAa3
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write
(D-Bank)
Read
(B-Bank)
Row Active
(D-Bank)
Row Active
(B-Bank)
: Don't care
* Note : tCDL should be met to complete write.
(December, 2009, Version 1.3)
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AMIC Technology, Corp.