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A43P8316G-95I 参数 Datasheet PDF下载

A43P8316G-95I图片预览
型号: A43P8316G-95I
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×16位×4银行同步DRAM [1M X 16 Bit X 4 Banks Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 42 页 / 502 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A43L2616B  
12. About Burst Type Control  
At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)  
BL=1,2,4,8 and full page wrap around.  
At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)  
BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting  
Sequential counting  
Basic  
MODE  
Interleave counting  
Every cycle Read/Write Command with random column address can realize  
Random Column Access.  
That is similar to Extended Data Out (EDO) Operation of convention DRAM.  
Random  
MODE  
Random column Access  
tCCD = 1 CLK  
13. About Burst Length Control  
At MRS A2,1,0 = “000”.  
At auto precharge, tRAS should not be violated.  
1
Basic  
MODE  
At MRS A2,1,0 = “001”.  
At auto precharge, tRAS should not be violated.  
At MRS A2,1,0 = “010”  
2
4
8
At MRS A2,1,0 = “011”.  
At MRS A9=”1”.  
Read burst = 1,2,4,8, full page/write Burst =1  
At auto precharge of write, tRAS should not be violated.  
Before the end of burst, Row precharge command of the same bank  
Stops read/write burst with Row precharge.  
Special  
BRSW  
MODE  
Interrupt  
RAS  
(Interrupted by Precharge)  
tRDL=1 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively  
Interrupt  
MODE  
During read/write burst with auto precharge,  
Before the end of burst, new read/write stops read/write burst and starts new  
read/write burst or block write.  
interrupt cannot be issued.  
RAS  
Interrupt  
CAS  
During read/write burst with auto precharge,  
interrupt can not be issued.  
CAS  
(December, 2009, Version 1.3)  
20  
AMIC Technology, Corp.  
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