A43E16161
Simplified Truth Table
Command
CKEn-1 CKEn
DQM BA A10 A9~A0 Notes
/AP
CAS
CS
WE
RAS
Register
Mode Register Set
1,2
H
H
X
X
L
L
L
L
L
L
L
L
X
L
OP CODE
OP CODE
Extended Mode Register Set
1,2
3
Refresh
Auto Refresh
Self
H
L
H
L
L
L
L
H
H
X
X
X
Entry
Exit
3
H
H
3
Refresh
L
H
X
X
X
H
L
X
L
X
H
X
H
3
4
Bank Active & Row Addr.
H
V
V
Row Addr.
Read &
Column Addr.
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
Column
Addr.
4
4,5
4
H
X
L
H
L
H
X
Write &
Column
Addr.
H
H
X
X
L
L
H
H
L
L
L
X
X
V
Column Addr.
H
4,5
6
Burst Stop
Precharge
H
X
Bank Selection
Both Banks
V
X
L
H
X
L
L
H
L
X
X
H
L
H
X
L
H
X
X
H
X
V
X
X
H
X
H
X
H
X
X
H
X
V
X
H
X
X
H
X
V
X
Entry
H
L
L
H
L
X
X
X
Clock Suspend or
Active Power Down
X
X
Exit
Entry
H
H
L
Precharge Power Down Mode
Exit
L
H
H
H
X
X
V
X
H
DQM
X
X
7
8
L
H
L
H
X
H
X
H
X
L
No Operation Command
Deep Power Down Entry
Deep Power Down Exit
H
L
L
X
X
X
X
H
X
X
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note : 1. OP Code: Operand Code
A0~A10, BA: Program keys. (@MRS, EMRS)
2. MRS can be issued only when all banks are at precharge state.
A new command can be issued after 2 clock cycle of MRS, EMRS.
3. Auto refresh functions is same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only when all banks are at precharge state.
4. BA: Bank select address.
5. During burst read or write with auto precharge, new read/write command cannot be issued.
Another bank read/write command can be issued at every burst length.
6. Bust stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)
but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
8. After Deep Power Down mode exit, a full new initialization of the memory device is mandatory.
PRELIMINARY (August, 2005, Version 0.0)
8
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
