A43E16161
Mode Register Filed Table to Program Modes
Register Programmed with MRS
Address
BA
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
0
RFU
W.B.L
TM
CAS Latency
BT
Burst Length
(Note 3)
(Note 1)
(Note 2)
Test Mode
Type
CAS Latency
Burst Type
Burst Length
A8 A7
A6 A5 A4
Latency
A3
Type
A2 A1 A0
BT=0
BT=1
0
0
1
0
1
0
Mode Register Set
0
0
0
0
0
1
0
1
0
Reserved
0
1
Sequential
Interleave
0
0
0
0
0
1
0
1
0
1
2
4
1
2
4
Vendor
Use
-
2
Only
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
3
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
8
8
Reserved
Reserved
Reserved
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
512(Full) Reserved
Write Burst Length
Length
A9
0
Burst
1
Single Bit
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. BA must be 0,0 to select the Mode Register (vs. the Extended Mode Register).
Extended Mode Register Table
BA
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
↓
1
↓
↓
↓
↓
Bank
↓
↓
↓
↓
↓
↓
PASR
↓
All have to be set to “0”
DS
0
Up/Down
(Note)
Driver Strength
Partial-Array Self Refresh:
Driver Strength
A7
A2
A1
A0
Banks to be Self-Refreshed
A6
A5
Driver Strength
0
0
1
1
0
1
0
1
Full
3/4
1/2
1/4
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
1
1
X
0
0
1
1
X
0
1
0
1
X
0
1
0
1
X
All banks (Bank 0, 1)
Reserved
Bank 0
Reserved
Reserved
All banks (Bank 0, 1)
Reserved
One bank (Bank 1)
Reserved
Reserved
Note: BA must be 1 to select the Extended Mode Register (vs. the Mode Register)
PRELIMINARY (August, 2005, Version 0.0)
9
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
