A43E06161
Burst Read Single Bit Write Cycle @Burst Length=2, BRSW
0
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CLOCK
CKE
High
CS
RAS
CAS
* Note 2
RAa
RAa
CAa
CBc
CAd
RBb
RBb
CAb
RAc
ADDR
BA
A10/AP
RAc
WE
DQM
DQ
(CL=2)
QAb0 QAb1
DBc0
DBc0
QAd0 QAd1
DAa0
DAa0
DQ
(CL=3)
QAb0 QAb1
QAd0 QAd1
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Row Active
(B-Bank)
Write with
Auto Precharge
(B-Bank)
Read with
Auto Precharge
(A-Bank)
Write
(A-Bank)
: Don't care
* Note : 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
The next cycle starts the precharge.
PRELIMINARY (July, 2005, Version 0.1)
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AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
