A416316B Series
AC Characteristics (continued)
(VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)
Std
-30
-35
-40
#
Symbol
Parameter
Unit Notes
Min. Max. Min. Max. Min. Max.
55
56
tOEH
tCPT
0
-
-
0
-
-
0
-
-
ns
ns
OE Command Hold Time
20
20
20
CAS Precharge Time
( CAS -before-RAS Counter Test)
Notes:
1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.
2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.
3. An initial pause of 200ms is required after power-up followed by any 8 RAS cycles before proper device operation is
achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before-RAS initialization cycles instead of 8
RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than
8ms).
4. AC Characteristics assume tT = 3ns. All AC parameters are measured with a load equivalent to one TTL loads and
50pF, VIL (min.) ³ GND and VIH (max.) £ VCC.
5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH and VIL.
6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference
point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.
7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.
8. Assumes three state test load (5pF and a 380W Thevenin equivalent).
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output
voltage levels.
11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only. If tWCS ³ tWCS (min.) and tWCH ³ tWCH (min.), the cycle is an early write cycle
and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ³ tRWD (min.) , tCWD ³
tCWD (min.) and tAWD ³ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from
the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is
indeterminate.
12. These parameters are referenced to
read-modify-write cycles.
and
leading edge in early write cycles and to WE leading edge in
LCAS
UCAS
13. Access time is determined by the longer of tAA or tCAC or tCPA.
14. tASC ³ tCP to achieve tPC (min.) and tCPA (max.) values.
15. These parameters are sampled and not 100% tested.
PRELIMINARY (November, 2000, Version 0.0)
9
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
