A29L040 Series
Timing Waveforms for
Polling (During Embedded Algorithms)
Data
tRC
Addresses
VA
VA
VA
tACC
tCE
CE
tCH
OE
tOE
tDF
tOEH
WE
tOH
High-Z
Valid Data
I/O7
Complement
Status Data
Complement True
High-Z
I/O0 - I/O6
Valid Data
Status Data
True
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Timing Waveforms for Toggle Bit (During Embedded Algorithms)
tRC
Addresses
CE
VA
VA
VA
VA
t
ACC
CE
t
tCH
t
OE
OE
t
DF
t
OEH
WE
t
OH
I/O6 , I/O2
Valid Status
(first read)
Valid Status
Valid Status
Valid Status
(second read)
(stop togging)
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
(September, 2011, Version 1.6)
19
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
