A29400 Series
The host system can detect whether a program or erase
operation is complete by reading the I/O7 ( Polling) and
I/O6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29400 is fully erased when
shipped from the factory.
sectors of memory. This can be achieved via programming
equipment.
Data
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program
data to, any other sector that is not selected for erasure.
True background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
The hardware
pin terminates any operation in
RESET
The hardware sector protection feature disables operations
for both program and erase in any combination of the
progress and resets the internal state machine to reading
array data.
Pin Configurations
nSOP
nTSOP (I)
1
RESET
WE
NC
RY/BY
A17
44
43
42
2
3
4
5
6
A8
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
A17
A7
A6
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
A16
BYTE
VSS
I/O15 (A-1)
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
A7
A6
A5
A9
41
40
39
A10
A11
A12
A4
A3
A2
A1
A0
7
38
8
A13
A14
A15
37
36
35
34
9
10
11
12
13
14
15
16
17
18
19
9
10
11
12
A29400V
A16
CE
33
32
31
30
29
28
27
26
BYTE
VSS
VSS
13
14
15
16
17
18
19
20
21
I/O9
I/O1
I/O8
OE
I/O0
I/O8
I/O1
I/O9
I/O2
I/O15 (A-1)
I/O7
A5
A4
A3
A2
A1
20
21
22
23
24
29
28
27
26
25
I/O0
OE
I/O14
I/O6
VSS
CE
A0
I/O13
I/O5
25
24
23
I/O12
I/O4
I/O10
I/O3
VCC
I/O11
22
PRELIMINARY
(February, 2001, Version 0.1)
2
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
