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A29400UM-70 参数 Datasheet PDF下载

A29400UM-70图片预览
型号: A29400UM-70
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×8位/ 256K ×16位CMOS 5.0伏只,引导扇区闪存 [512K X 8 Bit / 256K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 33 页 / 499 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A29400 Series  
Table 5. A29400 Command Definitions  
Bus Cycles (Notes 2 - 5)  
Third Fourth  
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data  
RA RD  
Command  
Sequence  
(Note 1)  
First  
Second  
Fifth  
Sixth  
Read (Note 6)  
Reset (Note 7)  
1
1
XXX F0  
555  
Word  
Byte  
2AA  
555  
2AA  
555  
AAA  
555  
Manufacturer ID  
4
4
AA  
55  
55  
90 X00  
37  
AAA  
Word  
Byte  
B3B0  
B0  
555  
AA  
AAA  
X01  
90  
Device ID,  
Top Boot Block  
555  
2AA  
555  
AAA  
X02  
Word  
Byte  
B331  
31  
555  
555 90  
AAA  
X01  
X02  
X03  
Device ID,  
Bottom Boot Block  
AA  
AA  
55  
4
4
AAA  
Word  
Byte  
555  
AAA  
555  
2AA  
555  
2AA  
555  
90  
Continuation ID  
55  
55  
7F  
X06  
AAA  
XX00  
XX01  
00  
(SA)  
X02  
555  
Word  
Sector Protect Verify  
(Note 9)  
4
AA  
90  
(SA)  
X04  
Byte  
AAA  
555  
AAA  
01  
Word  
Byte  
555  
AAA  
555  
AAA  
555  
AAA  
2AA  
555  
2AA  
555  
2AA  
555  
555  
A0  
Program  
4
6
6
AA  
AA  
AA  
55  
55  
55  
PA  
PD  
AA  
AA  
AAA  
Word  
Byte  
555  
80  
555  
AAA  
555  
AAA  
2AA  
555  
2AA  
555  
555  
Chip Erase  
55  
55  
10  
30  
AAA  
AAA  
Word  
Byte  
555  
Sector Erase  
80  
SA  
AAA  
Erase Suspend (Note 9)  
Erase Resume (Note 10)  
1
1
XXX B0  
XXX 30  
Legend:  
X = Don't care  
RA = Address of the memory location to be read.  
RD = Data read from location RA during read operation.  
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the  
whichever happens later.  
or  
pulse,  
CE  
WE  
PD = Data to be programmed at location PA. Data latches on the rising edge of  
or  
pulse, whichever happens first.  
CE  
WE  
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17 - A12 select a unique sector.  
Note:  
1. See Table 1 for description of bus operations.  
2. All values are in hexadecimal.  
3. Except when reading array or autoselect data, all bus cycles are write operation.  
4. Address bits A17 - A11 are don't cares for unlock and command cycles, unless SA or PA required.  
5. No unlock or command cycles required when reading array data.  
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high  
(while the device is providing status data).  
7. The fourth cycle of the autoselect command sequence is a read cycle.  
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information.  
9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.  
10. The Erase Resume command is valid only during the Erase Suspend mode.  
11. The time between each command cycle has to be less than 50ms.  
PRELIMINARY  
(February, 2001, Version 0.1)  
12  
AMIC Technology, Inc.