A29160 Series
Word/Byte Configuration
The
BYTE
pin determines whether the I/O pins I/O
15
-I/O
0
operate in the byte or word configuration. If the
BYTE
pin is
set at logic ”1”, the device is in word configuration, I/O
15
-I/O
0
are active and controlled by
CE
and
OE
.
If the
BYTE
pin is set at logic “0”, the device is in byte
configuration, and only I/O
0
-I/O
7
are active and controlled by
CE
and
OE
. I/O
8
-I/O
14
are tri-stated, and I/O
15
pin is used
as an input for the LSB(A-1) address function.
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O
7
- I/O
0
. Standard read cycle timings and I
CC
read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section for
timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the
OE
input.
The device enters the CMOS standby mode when the
CE
&
RESET
pins are both held at VCC
±
0.5V. (Note that this is a
more restricted voltage range than V
IH
.) If
CE
and
RESET
are held at V
IH
, but not within VCC
±
0.5V, the device will be
in the standby mode, but the standby current will be greater.
The device requires the standard access time (t
CE
) before it
is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I
CC3
and I
CC4
in the DC Characteristics tables represent the
standby current specification.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the
CE
and
OE
pins to V
IL
.
CE
is the power control and
selects the device.
OE
is the output control and gates array
data to the output pins.
WE
should remain at V
IH
all the time
during read operation. The
BYTE
pin determines whether
the device outputs array data in words and bytes. The
internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures that
no spurious alteration of the memory content occurs during
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The device
remains enabled for read access until the command register
contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
l
CC1
in the DC Characteristics table represents the active
current specification for reading array data.
Output Disable Mode
When the
OE
input is at V
IH
, output from the device is
disabled. The output pins are placed in the high impedance
state.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive
WE
and
CE
to V
IL
, and
RESET
: Hardware Reset Pin
The
RESET
pin provides a hardware method of resetting
the device to reading array data. When the system drives the
RESET
pin low for at least a period of t
RP
, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the
RESET
pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the
RESET
pulse.
When
RESET
is held at VSS
±
0.5V, the device draws
CMOS standby current (I
CC4
). If
RESET
is held at V
IL
but not
within VSS
±
0.5V, the standby current will be greater.
The
RESET
pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If
RESET
is asserted during a program or erase operation,
the RY/
BY
pin remains a “0” (busy) until the internal reset
operation is complete, which requires a time t
READY
(during
Embedded Algorithms). The system can thus monitor
RY/
BY
to determine whether the reset operation is
complete. If
RESET
is asserted when a program or erase
operation is not executing (RY/
BY
pin is “1”), the reset
operation is completed within a time of t
READY
(not during
6
OE
to V
IH
. For program operations, the
BYTE
pin
determines whether the device accepts program data in
bytes or words, Refer to “Word/Byte Configuration” for more
information. The device features an Unlock Bypass mode to
facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to
program a word or byte, instead of four.
The “Word / Byte Program Command Sequence” section has
details on programming data to the device using both
standard and Unlock Bypass command sequence. An erase
operation can erase one sector, multiple sectors, or the
entire device. The Sector Address Tables indicate the
address range that each sector occupies. A "sector address"
consists of the address inputs required to uniquely select a
sector. See the "Command Definitions" section for details on
erasing a sector or the entire chip, or suspending/resuming
the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O
7
- I/O
0
. Standard
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
I
CC2
in the DC Characteristics table represents the active
current specification for the write mode. The "AC
(November, 2010, Version 0.3)
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
