A29010A Series
"Autoselect Command Sequence" sections for more
information.
ICC2 in the Characteristics table represents the active current
specification for the write mode. The "AC Characteristics"
section contains timing specification tables and timing diagrams
for write operations.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the
and
pins to VIL.
is the power control and selects
CE
OE
CE
the device.
is the output control and gates array data to the
OE
output pins.
should remain at VIH all the time during read
WE
operation. The internal state machine is set for reading array
data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content
occurs during the power transition. No command is necessary
in this mode to obtain array data. Standard microprocessor read
cycles that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The device
remains enabled for read access until the command register
contents are altered.
Program and Erase Operation Status
During an erase or program operation, the system may check
the status of the operation by reading the status bits on I/O7 -
I/O0. Standard read cycle timings and ICC read specifications
apply. Refer to "Write Operation Status" for more information,
and to each AC Characteristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
See "Reading Array Data" for more information. Refer to the AC
Read Operations table for timing specifications and to the Read
Operations Timings diagram for the timing waveforms, lCC1 in
the DC Characteristics table represents the active current
specification for reading array data.
the high impedance state, independent of the
input.
OE
The device enters the CMOS standby mode when the
is
CE
Writing Commands/Command Sequences
held at VCC ± 0.5V. (Note that this is a more restricted voltage
range than VIH.) The device enters the TTL standby mode when
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
is held at VIH. The device requires the standard access
CE
time (tCE) before it is ready to read data.
memory), the system must drive
and
to VIL, and
CE OE
WE
If the device is deselected during erasure or programming, the
device draws active current until the operation is completed.
ICC3 in the DC Characteristics tables represents the standby
current specification.
to VIH. An erase operation can erase one sector, multiple
sectors, or the entire device. The Sector Address Tables
indicate the address range that each sector occupies. A "sector
address" consists of the address inputs required to uniquely
select a sector. See the "Command Definitions" section for
Output Disable Mode
details on erasing
a
sector or the entire chip, or
When the
input is at VIH, output from the device is
OE
suspending/resuming the erase operation.
disabled. The output pins are placed in the high impedance
state.
After the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then read
autoselect codes from the internal register (which is separate
from the memory array) on I/O7 - I/O0. Standard read cycle
timings apply in this mode. Refer to the "Autoselect Mode" and
Table 2. A29010A Block Sector Address Table
Sector
SA0
A16
0
A15
0
Sector Size (Kbytes)
Address Range
00000h - 07FFFh
08000h - 0FFFFh
10000h - 17FFFh
18000h - 1FFFFh
32
32
32
32
SA1
0
1
SA2
1
0
SA3
1
1
(May, 2014, Version 1.0)
5
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
