A25L80P
Figure 17-2. Power-Down and Voltage Drop
VCC
VCC(max)
VCC(min)
No Device Access Allowed
tPU
Device Access Allowed
VCC(low)
tPD
time
Table 6. Power-Up Timing and VWI Threshold
Symbol
Parameter
Min.
10
1
Max.
Unit
µs
1
tVSL
S
low
VCC(min) to
1
tPUW
Time delay to Write instruction
Write Inhibit Voltage
10
2
ms
V
1
VWI
1
Note: 1. These parameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains
00h (all Status Register bits are 0).
PRELIMINARY (May 2005, Version 0.0)
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AMIC Technology Corp.