A25L80P
Sector Erase (SE)
The Sector Erase (SE) instruction sets all bits to 1 (FFh).
Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
S
instruction is not executed. As soon as Chip Select ( ) is
driven High, the self-timed Sector Erase cycle (whose duration
is tBE) is initiated. While the Sector Erase cycle is in progress,
the Status Register may be read to check the value of the Write
In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Sector Erase (SE) instruction is executed only if all
Block Protect (BP2, BP1, BP0) bits are 0. The Sector Erase
(SE) instruction is ignored if one, or more, sectors are
protected.
The Sector Erase (SE) instruction is entered by driving Chip
S
Select ( ) Low, followed by the instruction code on Serial Data
S
Input (D). Chip Select ( ) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 11. Chip Select
S
(
) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Sector Erase
Figure 11. Sector Erase (SE) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
C
Instruction
24-Bit Address
22
3
0
23
21
2
1
D
MSB
Notes: Address bits A23 to A20 are Don’t Care.
PRELIMINARY (May 2005, Version 0.0)
16
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
