A25L20P/A25L10P/A25L05P Series
Hold Condition
The Hold (
communications with the device without resetting the clocking
sequence. However, taking this signal Low does not
terminate any Write Status Register, Program or Erase cycle
that is currently in progress.
Serial Clock (C) next goes Low. This is shown in Figure 3.
During the Hold condition, the Serial Data Output (DO) is high
impedance, and Serial Data Input (DIO) and Serial Clock (C)
are Don’t Care.
) signal is used to pause any serial
HOLD
Normally, the device is kept selected, with Chip Select (
)
S
To enter the Hold condition, the device must be selected, with
driven Low, for the whole duration of the Hold condition. This
is to ensure that the state of the internal logic remains
unchanged from the moment of entering the Hold condition.
Chip Select ( ) Low.
S
The Hold condition starts on the falling edge of the Hold
If Chip Select ( ) goes High while the device is in the Hold
S
condition, this has the effect of resetting the internal logic of
the device. To restart communication with the device, it is
(
) signal, provided that this coincides with Serial Clock
HOLD
(C) being Low (as shown in Figure 3.).
The Hold condition ends on the rising edge of the Hold
necessary to drive Hold (
) High, and then to drive
HOLD
(
) signal, provided that this coincides with Serial Clock
HOLD
Chip Select ( ) Low. This prevents the device from going
S
(C) being Low.
If the falling edge does not coincide with Serial Clock (C)
being Low, the Hold condition starts after Serial Clock (C)
next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after
back to the Hold condition.
Figure 3. Hold Condition Activation
C
HOLD
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
(August, 2007, Version 1.0)
7
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
