A25L20P/A25L10P/A25L05P Series
Figure 1. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA)
SDI
SCK
= (0, 0) or (1, 1)
C
DO DIO
C
DO DIO
C
DO DIO
Bus Master
(ST6, ST7, ST9,
ST10, Other)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S
W HOLD
S
W HOLD
S
W HOLD
Note: The Write Protect ( ) and Hold (
W
) signals should be driven, High or Low as appropriate.
HOLD
Figure 2. SPI Modes Supported
CPOL CPHA
0
1
0
1
C
C
DIO
DO
MSB
MSB
(August, 2007, Version 1.0)
4
AMIC Technology Corp.