A25L16P Series
Table 1. Protected Area Sizes
A25L16PT Top Boot Block
Status Register Content
Memory Content
BP2 Bit
BP1 Bit
BP0 Bit
Protected Area
Unprotected Area
0
1
0
1
0
1
none
All sectors (32 sectors: 0 to 31)
All sectors1 (32 sectors: 0 to 31)
none
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
2. The sector 31 include sector 31-0, sector 31-1, sector 31-2, sector 31-3 and sector 31-4.
A25L16PU Bottom Boot Block
Status Register Content
Memory Content
BP2 Bit
BP1 Bit
BP0 Bit
Protected Area
Unprotected Area
0
1
0
1
0
1
none
All sectors (32 sectors: 0 to 31)
All sectors1 (32 sectors: 0 to 31)
none
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
2. The sector 0 include sector 0-0, sector 0-1, sector 0-2, sector 0-3 and sector 0-4.
Hold Condition
with Serial Clock (C) being Low, the Hold condition ends
after Serial Clock (C) next goes Low. This is shown in Figure
3.
During the Hold condition, the Serial Data Output (DO) is
high impedance, and Serial Data Input (DIO) and Serial
Clock (C) are Don’t Care.
The Hold (
) signal is used to pause any serial
HOLD
communications with the device without resetting the
clocking sequence. However, taking this signal Low does not
terminate any Write Status Register, Program or Erase cycle
that is currently in progress.
To enter the Hold condition, the device must be selected,
Normally, the device is kept selected, with Chip Select (
)
S
with Chip Select ( ) Low.
S
The Hold condition starts on the falling edge of the Hold
driven Low, for the whole duration of the Hold condition. This
is to ensure that the state of the internal logic remains
unchanged from the moment of entering the Hold condition.
(
) signal, provided that this coincides with Serial Clock
HOLD
(C) being Low (as shown in Figure 3.).
The Hold condition ends on the rising edge of the Hold
If Chip Select ( ) goes High while the device is in the Hold
S
condition, this has the effect of resetting the internal logic of
the device. To restart communication with the device, it is
(
) signal, provided that this coincides with Serial Clock
HOLD
(C) being Low.
necessary to drive Hold (
) High, and then to drive
HOLD
If the falling edge does not coincide with Serial Clock (C)
being Low, the Hold condition starts after Serial Clock (C)
next goes Low. Similarly, if the rising edge does not coincide
Chip Select ( ) Low. This prevents the device from going
S
back to the Hold condition.
Figure 3. Hold Condition Activation
C
HOLD
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
PRELIMINARY (April, 2007, Version 0.6)
6
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
