A25L16P Series
Table 5. Protection Modes
Memory Content
SRWD
Bit
Write Protection of the
Status Register
W
Signal
Mode
Protected Area1
Unprotected Area1
1
0
1
0
0
1
Status Register is Writable (if the
Software WREN instruction has set the
Protected WEL bit) The values in the
Protected against Page
Program, Sector Erase and
Bulk Erase
Ready to accept Page
Program and Sector Erase
instructions
(SPM)
SRWD, BP2, BP1 and BP0 bits
can be changed
Status Register is Hardware write
protected The values in the
SRWD, BP2, BP1 and BP0 bits
cannot be changed
Hardware
Protected
(HPM)
Protected against Page
Program, Sector Erase and
Bulk Erase
Ready to accept Page
Program and Sector Erase
instructions
0
1
Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
consequence, all the data bytes in the memory area that
are software protected (SPM) by the Block Protect (BP2,
BP1, BP0) bits of the Status Register, are also hardware
protected against data modification.
The protection features of the device are summarized in Table 5.
When the Status Register Write Disable (SRWD) bit of the
Status Register is 0 (its initial delivery state), it is possible to
write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction, regardless of the whether Write Protect
Regardless of the order of the two events, the Hardware
Protected Mode (HPM) can be entered:
by setting the Status Register Write Disable (SRWD) bit
after driving Write Protect ( ) Low
(
) is driven High or Low.
W
When the Status Register Write Disable (SRWD) bit of the
Status Register is set to 1, two cases need to be considered,
W
or by driving Write Protect ( ) Low after setting the Status
W
Register Write Disable (SRWD) bit.
depending on the state of Write Protect ( ):
W
The only way to exit the Hardware Protected Mode (HPM) once
If Write Protect ( ) is driven High, it is possible to write to
W
entered is to pull Write Protect ( ) High.
the Status Register provided that the Write Enable Latch
(WEL) bit has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven Low, it is not possible to write
to the Status Register even if the Write Enable Latch (WEL)
bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are
rejected, and are not accepted for execution). As a
W
If Write Protect ( ) is permanently tied High, the Hardware
W
Protected Mode (HPM) can never be activated, and only the
Software Protected Mode (SPM), using the Block Protect (BP2,
BP1, BP0) bits of the Status Register, can be used.
PRELIMINARY (March, 2006, Version 0.2)
12
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
