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A25L10PU-F 参数 Datasheet PDF下载

A25L10PU-F图片预览
型号: A25L10PU-F
PDF下载: 下载PDF文件 查看货源
内容描述: 的2Mbit /为1Mbit /达512Kbit ,低电压,串行闪存的85MHz SPI总线接口 [2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface]
分类和应用: 闪存
文件页数/大小: 43 页 / 544 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A25L20P/A25L10P/A25L05P Series  
Table 16. AC Characteristics  
Alt.  
Parameter  
Min.  
Typ.  
Max.  
Unit  
Symbol  
fC  
fC  
Clock Frequency for the following instructions: FAST_READ,  
PP, SE, BE, DP, RES, RDID, WREN, WRDI, RDSR, WRSR  
D.C.  
85  
MHz  
fR  
tCH  
tCL  
Clock Frequency for READ instructions  
Clock High Time  
D.C.  
6
50  
MHz  
ns  
1
1
tCLH  
tCLL  
Clock Low Time  
5
ns  
2
2
tCLCH  
tCHCL  
tSLCH  
Clock Rise Time3 (peak to peak)  
Clock Fall Time3 (peak to peak)  
0.1  
0.1  
5
V/ns  
V/ns  
ns  
tCSS  
S
S
Active Setup Time (relative to C)  
Not Active Hold Time (relative to C)  
tCHSL  
5
ns  
tDVCH  
tCHDX  
tCHSH  
tDSU  
tDH  
Data In Setup Time  
Data In Hold Time  
5
5
5
ns  
ns  
ns  
S
S
S
Active Hold Time (relative to C)  
Not Active Setup Time (relative to C)  
Deselect Time  
tSHCH  
tSHSL  
5
ns  
ns  
tCSH  
100  
2
tSHQZ  
tCLQV  
tCLQX  
tHLCH  
tDIS  
tV  
Output Disable Time  
Clock Low to Output Valid  
Output Hold Time  
8
8
ns  
ns  
ns  
ns  
tHO  
0
5
Setup Time (relative to C)  
HOLD  
HOLD  
tCHHH  
5
ns  
Hold Time (relative to C)  
tHHCH  
tCHHL  
HOLD Setup Time (relative to C)  
HOLD Hold Time (relative to C)  
HOLD to Output Low-Z  
5
5
ns  
ns  
ns  
ns  
2
tHHQX  
tLZ  
8
8
2
tHLQZ  
tHZ  
to Output High-Z  
HOLD  
4
4
tWHSL  
tSHWL  
Write Protect Setup Time  
Write Protect Hold Time  
20  
ns  
ns  
µs  
100  
2
tDP  
3
S
S
S
High to Deep Power-down Mode  
2
2
tRES1  
tRES2  
30  
30  
µs  
µs  
High to Standby Mode without Electronic Signature Read  
High to Standby Mode with Electronic Signature Read  
tW  
tpp  
tSE  
Write Status Register Cycle Time  
Page Program Cycle Time  
100  
3
300  
5
ms  
ms  
s
Sector Erase Cycle Time  
1
3
Bulk Erase Cycle Time of A25L20P  
Bulk Erase Cycle Time of A25L10P  
Bulk Erase Cycle Time of A25L05P  
6
8
s
tBE  
4
6
s
3
5
s
Note: 1. tCH + tCL must be greater than or equal to 1/ fC  
2. Value guaranteed by characterization, not 100% tested in production.  
3. Expressed as a slew-rate.  
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.  
(August, 2007, Version 1.0)  
32  
AMIC Technology Corp.  
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