A25L20P/A25L10P/A25L05P Series
2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory
With 85MHz SPI Bus Interface
FEATURES
2Mbit / 1Mbit / 512Kbit of Flash Memory
Flexible Sector Architecture
- 25L20P: (4/4/8/16/32)KB/64x3 KB
- 25L10P: (4/4/8/16/32)KB/64x1KB
- 25L05P: (4/4/8/16/32)KB
Bulk Erase (typical)
- 25L20P (2M) in 6s
- A25L10P (1M) in 4s
- A25L05P (512K) in 3s
Sector Erase (512 Kbit) in 1s (typical)
Page Program (up to 256 Bytes) in 3ms (typical)
2.7 to 3.6V Single Supply Voltage
SPI Bus Compatible Serial Interface
85MHz Clock Rate (maximum)
Deep Power-down Mode 1µA (typical)
Top or Bottom boot block configuration available
Electronic Signatures
-
JEDEC Standard Two-Byte Signature
A25L20P: (2012h, Bottom) or (2022h, top)
A25L10P: (2011h, Bottom) or (2021h, top)
A25L05P: (2010h, Bottom) or (2020h, top)
-
RES Instruction, One-Byte, Signature, for backward
compatibility
A25L20P (11h)
A25L10P (10h)
A25L05P (05h)
Package options
-
8-pin SOP (150mil or 209mil), 8-pin DIP (300mil) or 8-pin
QFN
- All Pb-free (Lead-free) products are RoHS compliant
GENERAL DESCRIPTION
The A25L20P/A25L10P/A25L05P are 2M/1M/512 bit Serial
Flash Memory, with advanced write protection mechanisms,
accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using
the Page Program instruction.
The memory is organized as 4/2/1 sectors, each containing 256
pages. Each page is 256 bytes wide. Thus, the whole memory
can be viewed as consisting of 1024/512/256 pages, or 262,144
/131,072/65,536 bytes.
The whole memory can be erased using the Bulk Erase
instruction, or a sector at a time, using the Sector Erase
instruction.
Pin Configurations
SO8 Connections
A25L20P/
A25L10P/
A25L05P
S
DO
W
V
SS
1
2
3
4
8 V
CC
7 HOLD
6 C
5 DIO
S
DO
W
V
SS
DIP8 Connections
A25L20P/
A25L10P/
A25L05P
1
2
3
4
8 V
CC
7 HOLD
6 C
5 DIO
QFN8 Connections
A25L20P/
A25L10P/
A25L05P
S
DO
W
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
C
DIO
(August, 2007, Version 1.0)
1
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
