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A25L10PT-UF 参数 Datasheet PDF下载

A25L10PT-UF图片预览
型号: A25L10PT-UF
PDF下载: 下载PDF文件 查看货源
内容描述: 的2Mbit /为1Mbit /达512Kbit ,低电压,串行闪存的85MHz SPI总线接口 [2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 43 页 / 544 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A25L20P/A25L10P/A25L05P Series  
edge of Serial Clock (C). Then, the 8-bit Electronic Signature,  
stored in the memory, is shifted out on Serial Data Output  
(DO), each bit being shifted out during the falling edge of  
Serial Clock (C).  
The instruction sequence is shown in Figure 17.  
The Release from Deep Power-down and Read Electronic  
Signature (RES) instruction is terminated by driving Chip  
Release from Deep Power-down and Read  
Electronic Signature (RES)  
Once the device has entered the Deep Power-down mode,  
all instructions are ignored except the Release from Deep  
Power-down and Read Electronic Signature (RES)  
instruction. Executing this instruction takes the device out of  
the Deep Power-down mode.  
S
Select ( ) High after the Electronic Signature has been read  
The instruction can also be used to read, on Serial Data  
Output (DO), the 8-bit Electronic Signature, whose value for  
the A25L20P is 11h, A25L10P is 10h, and A25L05P is 05h.  
at least once. Sending additional clock cycles on Serial Clock  
S
(C), while Chip Select ( ) is driven Low, cause the  
Electronic Signature to be output repeatedly.  
Except while an Erase, Program or Write Status Register  
cycle is in progress, the Release from Deep Power-down and  
Read Electronic Signature (RES) instruction always provides  
access to the 8-bit Electronic Signature of the device, and  
can be applied even if the Deep Power-down mode has not  
been entered.  
S
When Chip Select ( ) is driven High, the device is put in the  
Stand-by Power mode. If the device was not previously in the  
Deep Power-down mode, the transition to the Stand-by  
Power mode is immediate. If the device was previously in the  
Deep Power-down mode, though, the transition to the Stand-  
Any Release from Deep Power-down and Read Electronic  
Signature (RES) instruction while an Erase, Program or Write  
Status Register cycle is in progress, is not decoded, and has  
no effect on the cycle that is in progress.  
S
by Power mode is delayed by tRES2, and Chip Select (  
)
must remain High for at least tRES2 (max), as specified in AC  
Characteristics Table . Once in the Stand-by Power mode,  
the device waits to be selected, so that it can receive, decode  
and execute instructions.  
S
The device is first selected by driving Chip Select ( ) Low.  
The instruction code is followed by 3 dummy bytes, each bit  
being latched-in on Serial Data Input (DIO) during the rising  
Figure 17. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and  
Data-Out Sequence  
S
6
0
1
2
3
4
5
7
8
9 10  
28 29 30 31 32 33 34 35 36 37 38  
C
DIO  
DO  
tRES2  
Instruction  
3 Dummy Bytes  
21  
23  
2
1
0
22  
3
MSB  
High Impedance  
5
4
1
0
6
3
2
7
MSB  
Deep Power-down Mode  
Stand-by Mode  
Note: The value of the 8-bit Electronic Signature, for the A25L20P is 11h, A25L10P is 10h, and A25L05P is 05h.  
(August, 2007, Version 1.0)  
25  
AMIC Technology Corp.  
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