A25L016 Series
Table 15. AC Characteristics
Alt.
Parameter
Min.
Typ.
Max.
Unit
Symbol
fC
fC
Clock Frequency for the following instructions: FAST_READ,
PP, SE, BE, DP, RES, RDID, WREN, WRDI, RDSR, WRSR
D.C.
100
MHz
fR
tCH
tCL
Clock Frequency for READ instructions
Clock High Time
D.C.
6
50
MHz
ns
1
1
tCLH
tCLL
Clock Low Time
5
ns
2
2
tCLCH
tCHCL
tSLCH
Clock Rise Time3 (peak to peak)
Clock Fall Time3 (peak to peak)
0.1
0.1
5
V/ns
V/ns
ns
tCSS
S
S
Active Setup Time (relative to C)
Not Active Hold Time (relative to C)
tCHSL
5
ns
tDVCH
tCHDX
tCHSH
tDSU
tDH
Data In Setup Time
Data In Hold Time
5
5
5
ns
ns
ns
S
S
S
Active Hold Time (relative to C)
Not Active Setup Time (relative to C)
Deselect Time
tSHCH
tSHSL
5
ns
ns
tCSH
100
2
tSHQZ
tCLQV
tCLQX
tHLCH
tDIS
tV
Output Disable Time
Clock Low to Output Valid
Output Hold Time
8
8
ns
ns
ns
ns
tHO
0
5
Setup Time (relative to C)
HOLD
HOLD
tCHHH
5
ns
Hold Time (relative to C)
tHHCH
tCHHL
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD to Output Low-Z
5
5
ns
ns
ns
ns
2
tHHQX
tLZ
8
8
2
tHLQZ
tHZ
to Output High-Z
HOLD
4
4
tWHSL
tSHWL
Write Protect Setup Time
Write Protect Hold Time
20
ns
ns
µs
100
2
tDP
3
S
S
S
High to Deep Power-down Mode
2
2
tRES1
tRES2
30
30
µs
µs
High to Standby Mode without Electronic Signature Read
High to Standby Mode with Electronic Signature Read
tW
tpp
tSE
tBE
tCE
Write Status Register Cycle Time
Page Program Cycle Time
Sector Erase Cycle Time
Block Erase Cycle Time
Chip Erase Cycle Time
5
2
20
3
ms
ms
s
0.08
0.5
16
0.2
2
s
32
s
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
(March, 2012, Version 2.0)
33
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
