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A25L080Q4-UFG 参数 Datasheet PDF下载

A25L080Q4-UFG图片预览
型号: A25L080Q4-UFG
PDF下载: 下载PDF文件 查看货源
内容描述: 16Mbit的低电压,串行闪存的100MHz统一4KB扇区 [16Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors]
分类和应用: 闪存
文件页数/大小: 43 页 / 681 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A25L016 Series  
POWER-UP AND POWER-DOWN  
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tPUW after VCC passed the VWI threshold  
tVSL afterVCC passed the VCC(min) level  
At Power-up and Power-down, the device must not be  
S
selected (that is Chip Select ( ) must follow the voltage  
These values are specified in Table 8.  
If the delay, tVSL, has elapsed, after VCC has risen above  
applied on VCC) until VCC reaches the correct value:  
­
­
VCC (min) at Power-up, and then for a further delay of tVSL  
VSS at Power-down  
V
CC(min), the device can be selected for READ instructions  
even if the tPUW delay is not yet fully elapsed.  
At Power-up, the device is in the following state:  
S
Usually a simple pull-up resistor on Chip Select ( ) can be  
used to insure safe and proper Power-up and Power-down.  
To avoid data corruption and inadvertent write operations  
during power up, a Power On Reset (POR) circuit is included.  
The logic inside the device is held reset while VCC is less than  
the POR threshold value, VWI – all operations are disabled,  
and the device does not respond to any instruction.  
­
­
The device is in the Standby mode (not the Deep  
Power-down mode).  
The Write Enable Latch (WEL) bit is reset.  
Normal precautions must be taken for supply rail decoupling,  
to stabilize the VCC feed. Each device in a system should  
have the VCC rail decoupled by a suitable capacitor close to  
the package pins. (Generally, this capacitor is of the order of  
0.1µF).  
At Power-down, when VCC drops from the operating voltage,  
to below the POR threshold value, VWI, all operations are  
disabled and the device does not respond to any instruction.  
(The designer needs to be aware that if a Power-down occurs  
while a Write, Program or Erase cycle is in progress, some  
data corruption can result.)  
Moreover, the device ignores all Write Enable (WREN), Page  
Program (PP), Sector Erase (SE), Block Erase (BE), Chip  
Erase (CE) and Write Status Register (WRSR) instructions  
until a time delay of tPUW has elapsed after the moment that  
VCC rises above the VWI threshold. However, the correct  
operation of the device is not guaranteed if, by this time, VCC  
is still below VCC(min). No Write Status Register, Program or  
Erase instructions should be sent until the later of:  
Figure 21. Power-up Timing  
VCC  
VCC(max)  
VCC(min)  
tPU  
Full Device Access  
time  
(March, 2012, Version 2.0)  
28  
AMIC Technology Corp.  
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