欢迎访问ic37.com |
会员登录 免费注册
发布采购

A25L016O-UFQ 参数 Datasheet PDF下载

A25L016O-UFQ图片预览
型号: A25L016O-UFQ
PDF下载: 下载PDF文件 查看货源
内容描述: 16Mbit的低电压,串行闪存的100MHz统一4KB扇区 [16Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors]
分类和应用: 闪存
文件页数/大小: 43 页 / 681 K
品牌: AMICC [ AMIC TECHNOLOGY ]
 浏览型号A25L016O-UFQ的Datasheet PDF文件第23页浏览型号A25L016O-UFQ的Datasheet PDF文件第24页浏览型号A25L016O-UFQ的Datasheet PDF文件第25页浏览型号A25L016O-UFQ的Datasheet PDF文件第26页浏览型号A25L016O-UFQ的Datasheet PDF文件第28页浏览型号A25L016O-UFQ的Datasheet PDF文件第29页浏览型号A25L016O-UFQ的Datasheet PDF文件第30页浏览型号A25L016O-UFQ的Datasheet PDF文件第31页  
A25L016 Series  
edge of Serial Clock (C). Then, the 8-bit Electronic Signature,  
stored in the memory, is shifted out on Serial Data Output  
(DO), each bit being shifted out during the falling edge of  
Serial Clock (C).  
The instruction sequence is shown in Figure 19.  
The Release from Deep Power-down and Read Electronic  
Signature (RES) instruction is terminated by driving Chip  
Release from Deep Power-down and Read  
Electronic Signature (RES)  
Once the device has entered the Deep Power-down mode,  
all instructions are ignored except the Release from Deep  
Power-down and Read Electronic Signature (RES)  
instruction. Executing this instruction takes the device out of  
the Deep Power-down mode.  
S
Select ( ) High after the Electronic Signature has been read  
The instruction can also be used to read, on Serial Data  
Output (DO), the 8-bit Electronic Signature, whose value for  
A25L016 is 14h.  
at least once. Sending additional clock cycles on Serial Clock  
S
(C), while Chip Select ( ) is driven Low, cause the  
Electronic Signature to be output repeatedly.  
Except while an Erase, Program or Write Status Register  
cycle is in progress, the Release from Deep Power-down and  
Read Electronic Signature (RES) instruction always provides  
access to the 8-bit Electronic Signature of the device, and  
can be applied even if the Deep Power-down mode has not  
been entered.  
S
When Chip Select ( ) is driven High, the device is put in the  
Stand-by Power mode. If the device was not previously in the  
Deep Power-down mode, the transition to the Stand-by  
Power mode is immediate. If the device was previously in the  
Deep Power-down mode, though, the transition to the Stand-  
Any Release from Deep Power-down and Read Electronic  
Signature (RES) instruction while an Erase, Program or Write  
Status Register cycle is in progress, is not decoded, and has  
no effect on the cycle that is in progress.  
S
by Power mode is delayed by tRES2, and Chip Select (  
)
must remain High for at least tRES2 (max), as specified in AC  
Characteristics Table . Once in the Stand-by Power mode,  
the device waits to be selected, so that it can receive, decode  
and execute instructions.  
S
The device is first selected by driving Chip Select ( ) Low.  
The instruction code is followed by 3 dummy bytes, each bit  
being latched-in on Serial Data Input (DIO) during the rising  
Figure 19. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and  
Data-Out Sequence  
S
6
0
1
2
3
4
5
7
8
9 10  
28 29 30 31 32 33 34 35 36 37 38  
C
DIO  
DO  
tRES2  
Instruction  
3 Dummy Bytes  
21  
23  
2
1
0
22  
3
MSB  
High Impedance  
5
4
1
0
6
3
2
7
MSB  
Deep Power-down Mode  
Note: The value of the 8-bit Electronic Signature is 14h.  
Stand-by Mode  
(March, 2012, Version 2.0)  
26  
AMIC Technology Corp.  
 复制成功!