A25LQ080 Series
POWER-UP AND POWER-DOWN
-
tPUW after VCC passed the VWI threshold
tVSL afterVCC passed the VCC(min) level
At Power-up and Power-down, the device must not be
S
selected (that is Chip Select ( ) must follow the voltage
These values are specified in Table 9.
If the delay, tVSL, has elapsed, after VCC has risen above
applied on VCC) until VCC reaches the correct value:
VCC (min) at Power-up, and then for a further delay of tVSL
VSS at Power-down
V
CC(min), the device can be selected for Read instructions
even if the tPUW delay is not yet fully elapsed.
At Power-up, the device is in the following state:
S
Usually a simple pull-up resistor on Chip Select ( ) can be
used to insure safe and proper Power-up and Power-down.
To avoid data corruption and inadvertent write operations
during power up, a Power On Reset (POR) circuit is included.
The logic inside the device is held reset while VCC is less than
the POR threshold value, VWI – all operations are disabled,
and the device does not respond to any instruction.
The device is in the Standby mode (not the Deep
Power-down mode).
The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail decoupling,
to stabilize the VCC feed. Each device in a system should
have the VCC rail decoupled by a suitable capacitor close to
the package pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when VCC drops from the operating voltage,
to below the POR threshold value, VWI, all operations are
disabled and the device does not respond to any instruction.
(The designer needs to be aware that if a Power-down occurs
while a Write, Program or Erase cycle is in progress, some
data corruption can result.)
Moreover, the device ignores all Write Enable (WREN),
Program OTP (POTP), Page Program (PP), Dual Input Fast
Program (DIFP), Quad Input Fast Program (QIFP), Sector
Erase (SE), Block Erase (BE), Chip Erase (CE) and Write
Status Register (WRSR) instructions until a time delay of tPUW
has elapsed after the moment that VCC rises above the VWI
threshold. However, the correct operation of the device is not
guaranteed if, by this time, VCC is still below VCC(min). No
Write Status Register, Program or Erase instructions should
be sent until the later of:
Figure 31. Power-up Timing
VCC
VCC(max)
VCC(min)
Reset
State
tVSL
Read
Access
allowed
Full Device Access
VWI
tPUW
time
(April, 2016, Version 1.0)
45
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
