A23L9308 Series
Timing Waveforms
Propagation Delay from Address (CE/ CE = Active, OE/ OE= Active)
tCYC
ADDRESS
INPUTS
VALID
tAA
tOH
VALID
DATA OUT
Propagation Delay from Chip Enable or Output Enable (Address Valid)
CHIP
ENABLE
VALID
tACE
OUTPUT
ENABLE
VALID
tAOE
tHZ
tLZ
VALID
DATA OUT
tLZ
AC Test Conditions
Applied Voltage
Input Pulse Levels
2.7V~3.6V
0.4V to 2.4V
10 ns
Input Rise and Fall Time
VIN = 1.5V
VOUT = 1.5V
Timing Measurement Reference Level
Output Load
1 TTL gate and CL = 100pF
PRELIMINARY
(October, 2001, Version 0.0)
6
AMIC Technology, Inc.