INPUT VOLTAGE AT
DIGITAL LOW (INPUT
CLOCKS SP AND CP)
CLOCK FREQUENCY
VIL
0
0.8
V
FREQ (3)
DUTY (4)
5.0
6.0
75
MHz
%
CLOCK PULSE HIGH DUTY
CYCLE
CLOCK HIGH DURATION
INTEGRATION TIME
25
TPW (3)(5)
TINT
83.3
100
ns, at 50%Duty
Typical, Tested
@ 5.0 MHz
Clock
192µs/line
160µs/line
Minimum,
Tested @ 6.0
MHz Clock
0C
OPERATING
TOP (6)
25
50
TEMPERATURE
Notes:
Note (1) Vpavg is a symbol representing the average value of every pixel in the complete line
scan. Vp(n) is the pixel amplitude of nth pixel in a line scan. This measurement is taken
with the image array under a uniform light exposure. The typical output is specified with
a uniform input light exposure of 0.5µJ/cm2 from a blue Led light source.
Note (2) Two saturated video output levels are specified. One is at the video signal’s output
amplifier, VSATA, and the other is at the input of the amplifier. In almost all
applications, because the integration time is usually too short, there is not enough
exposure time to saturate the array sensors. Accordingly, each output amplifier is fixed
with a gain of ≅ 4.5.
Note (3) FREQ is generally fixed for any application for the following reasons: One is the
exposure time. With a given light power, the exposure time of the sensor depends on
integration time, TINT, and in many of the applications it uses a clock count down
circuits to generate the SP, shift register start pulse, hence, it will be related to the clock
frequency. The second is the shape of the video output pulse. Because of the output
video is in pulse charge packets, the signals are processed on the output video line of
the sensors. Hence, the signal shape depends greatly upon the amplifier
configurations. Please refer to the referenced PI3039 Data Sheet. It has some brief
outline application notes. Under Note 6 in page 6 there is a discussion on video pulse
shapes. On page 8, 9 and 10 there are discussions on the three types of signal output
stages.
Note (4) DUTY is the ratio of the clock’s pulse width over its pulse period. Because the video
pixel output resets during the clock pulse’s high period and because the reset requires
a finite resetting time, the clock duty cycle is recommended to operate within the
following limits. See referenced data sheet in above note 3. Noting that the larger the
DUTY, the less the signal amplitude, while too short of clock pulse will not provide
enough video reset time and leaves residual charges, the recommended DUTY is 25%
for frequencies < 5MHz and 50% for frequencies > 5MHz.
Note (5) TINT is determined by time interval between two start pulses, SP. Hence, if SP is
generated from a clock count down circuit, it will be directly proportional to clock
frequency. And it will be synchronous with the clock frequency. The longest integration
time is determined by the degree of leakage current degradation that can be tolerated
by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user
can use his discretion and determine the desired tolerance level for the given system.
PAGE 4 OF 22 - PI616MC-AS, 12/20/02
AMI [ AMI SEMICONDUCTOR ]
