Switching Characteristics (25°C)
to
CP
tprh
tdh
SP
tds
Vout
tsh
tdl
tw
MODULE TIMING DIAGRAM
Figure 3
The Switching Characteristics (25°C) for the I/O clocks are shown in the diagram below.
For the timing symbol definitions see the following table below the timing diagram.
Item
Clock cycle time
Clock pulse width
Clock duty cycle
Prohibit crossing time
of Start Pulse
(1)
Data setup time
Data hold time
Signal delay time
Signal settling time
Symbol
to
tw
tprh
tds
tdh
tdl
tsh
Min.
0.20
50
25
0
20
0
20
100
Typical
Max.
2.0
75
Units
µs
ns
%
ns
ns
ns
ns
ns
Table 6. Timing Symbol’s Definition and Timing Values.
Note:
(1) "Prohibit crossing of start pulse" is to indicate that the start pulse should not be
active high between any two consecutive high going clock pulse or two
consecutive low going clock pulses. See the timing diagram. Only one high going
clock under the active high start pulse initiates the internal shift register, and it
must not be active over two high going clocks. All low going clock pulses will not
initiate the shift register, but to ensure that the start pulse will not be actively high
during two consecutive high going clocks, the circuit should be design to keep the
start pulse active only for one low going clock cycle.
PAGE 6 OF 7 - PI400M-A4, 11-15-00
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