to
CP
tprh
tdh
SP
tds
Vout
tsh
tw
tdl
MODULE TIMING DIAGRAM
Figure 4
Item
Clock cycle time
Clock pulse width
Clock duty cycle
Prohibit crossing time
of Start Pulse
(1)
Data setup time
Data hold time
Signal delay time
Signal settling time
Symbol
to
tw
tprh
tds
tdh
tdl
tsh
Min.
0.20
50
25
0
20
0
20
100
Typical
Max.
4.0
75
Units
µs
ns
%
ns
ns
ns
ns
ns
Table 7. Timing Symbol’s Definition and Timing Values
.
Note1:
"Prohibit crossing of start pulse" is to indicate that the start pulse should not be active high
between any two consecutive clock pulse, specifically, between two consecutive low going clock
pulses. See the timing diagram. All falling clock edges under a active high start pulse loads the
internal shift register, therefore the start pulse must be active over only one falling clock edge.
High start pulse over all rising clock edge is ignored by the shift register. One simple way to
ensure that the start pulse will not be actively high during two consecutive falling clock edge is to
generate the start pulse on a rising clock edge and terminate it on the following rising clock edge.
PAGE 9 OF 10 - PI227/228/229, 01-31-04
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