MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
De ta ile d Fu n ctio n a l De scrip tio n
O ve rvie w
CPU
(pseudo)static RAMs. The bus interface
2. S interface of MTC-20276/ 20277
INT, GCI-S
3. Interface to analog devices such as
MTK-40131 short-haul POTS
chipset, GCI-A
The integrated ARM7TDMI CPU will
generally use the 16-bit data bus
mode ‘Thumb’. The external bus
interface supports 16- or 32-bit
transfers, multiplexed to 16- or 8 bits.
Access to the on-chip SRAM can take
place as 8, 16, or 32 bit transfers (it
thus supports the full performance of
the ARM CPU). The CPU will generally
run at the clock frequency set by the
crystal oscillator (15.36 Mhz).
However, a programmable divider is
provided to allow software control of
the processor speed, and therefore the
power consumption.
logic includes a programmable WAIT
STATE generator, to allow access to
slow external memory or peripherals.
Bus timing is to allow zero wait state
execution (with fast off-chip memory)
at a CPU clock of 15 Mhz. 1 kbyte of
fast (0 wait-state with 32 bit access),
on-chip static RAM is included.
In reality, all three GCI ports are
identical - the allocation to U, S, and
A (analog) is arbitrary, for clarity only.
A programmable Chip-Select (“CS”)
decoder defines the external memory-
map - the default map ensures that the
CPU can start up from reset by
The U interface block of the INT will
always provide the GCI clocks
(master) when active. (This can be
achieved by issuing the AWAKE
command on the GCI C/ I bits to the U
interface, which activates the timing
generator of the U interface without
actually initiating transmission).
All other GCI buses will generally be
slaved to this one. In applications
where the use of the U interface is not
mandatory (e.g. in a micro-PABX
system which allows internal calling
without U activation), an internal GCI
clock source can be selected. An
integrated PLL system may be enabled
to allow the internally generated GCI
clocks to track and lock to the U GCI
clock, should this become active in the
course of operation.
enabling ROM at address 0. It
provides for seven external memory
ranges to be individually decoded.
With regard to EMC requirements, the
slope of the memory bus transitions is
controlled, in a manner consistent with
achieving the required bus transfer
speed. Each CS memory range has
programmable wait-states.
Clo ck g e n e ra tio n a n d co n tro l
A master clock oscillator, based on
an external crystal of 15.36Mhz,
is provided. This provides an output at
the crystal frequency for use by the
ISDN chip (INTT or INTQ).
A programmable divider allows lower
frequencies to be output, as required.
The CPU clock frequency is SW
selectable, allowing the power-
consumption to be reduced at times
when full processing speed is not
required.
An external interrupt request pin
allows external peripheral devices
to communicate asynchronously with
the CPU.
3 -w a y GCI in te rfa ce
(Terminology. ‘DOWNSTREAM’ refers
to the transfer of data coming from the
U interface towards the S or Analog
interfaces in an ISDN application.
Upstream is the direction from the S
or analog interfaces towards the U.)
Me m o ry b u s
The external memory bus supports
either 8-bit (for low cost) or 16 bit
(high-speed) memory systems. It allows
read/ write access to off-chip memory
and I/ O resources, and includes a
simple to use on-chip memory
decoding scheme to minimize external
logic. It is designed to interface to
standard FLASH EEPROM and
The device provides for three
GCI ports: normally allocated
as follows:
1. U interface of MTC-20276/ 20277
INT, GCI-U
10
AMI [ AMI SEMICONDUCTOR ]
