FS6322-02
Three-PLL Clock Generator IC
1.0
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Features
2.0
Description
Three PLLs with deep reference, feedback, and post
dividers to provide precision clock frequencies
Multiple outputs provide several clocking options
Suspend feature shuts down a selection of PLLs and
outputs for power conservation
Outputs may be tristated for board testing
S0 and S1 frequency select inputs modify output fre-
quencies for design flexibility
Glitch-free slewing of CLK_CPU output enables
downstream PLLs to remain locked
5V to 3.3V operation
Accepts 5 to 30MHz crystals
Custom frequency patterns, pinouts, and packages
are available. Contact your local AMI Sales Repre-
sentative for more information.
The FS6322 is a ROM-based CMOS clock generator IC
designed to minimize cost and component count in a va-
riety of electronic systems.
Three low-jitter phase-locked loops (PLLs) drive up to five
low-skew clock outputs to provide a high degree of flexi-
bility. A buffered copy of the reference clock is also avail-
able. The device is packaged in a 16-pin SOIC to mini-
mize board space.
Figure 1: Pin Configuration
CLK_C
VDD
VSS
XIN
XOUT
XBUF
CLK_D
CLK_CPU
1
2
3
16
15
14
OE
SUSPEND#
VDD
S1
S0
VSS
CLK_A
CLK_B
FS6322
4
5
6
7
8
13
12
11
10
9
16-pin (0.150”) SOIC
Figure 2: Block Diagram
OE
XIN
XOUT
Crystal
Oscillator
PLL A
XBUF
CLK_A
CLK_B
PLL B
Clock
Logic
CLK_C
CLK_D
CLK_CPU
S1:S0
SUSPEND#
PLL CPU
FS6322
This document contains information on a product under development. American Microsystems, Inc. reserves the right to change or discontinue this product without notice.
ISO9001
3.1.02
AMI [ AMI SEMICONDUCTOR ]
