AMIS-39100: Octal High Side Driver with Protection
Data Sheet
8.7 SPI Interface
The serial peripheral interface (SPI) is used to allow an external microcontroller (MCU) to communicate with the device. The AMIS-
39100 acts always as a slave and it can’t initiate any transmission.
8.7.1. SPI Transfer Format and Pin Signals
The SPI block diagram and timing characteristics are shown in Figure 6 and Figure 7.
During an SPI transfer, data is simultaneously sent to and received from the device. A serial clock line (CLK) synchronizes shifting and
sampling of the information on the two serial data lines (DIN and DOUT). DOUT signal is the output from the AMIS-39100 to the
external MCU and DIN signal is the input from the MCU to the AMIS-39100. The WR-pin selects the AMIS-39100 for communication
and can also be used as a chip select (CS) in a multiple-slave system. The WR-pin is active low. If AMIS-39100 is not selected, DOUT
is in high impedance state and it does not interfere with SPI bus activities. Since AMIS-39100 always shifts data out on the rising edge
and samples the input data also on the rising edge of the CLK signal, the MCU SPI port must be configured to match this operation.
SPI clock idles high between the transferred bytes.
The diagram in Figure 7 represents the SPI timing diagram for 8-bit communication. Communication starts with a falling edge on the
WR-pin that latches the status of the diagnostic register into the SPI output register. Subsequently, the CMD_x bits – representing the
newly requested driver status – are shifted into the input register and simultaneously, the DIAG_x bits – representing the actual output
status – are shifted out. The bits are shifted with x=1 first and ending with x=8. At the rising edge of the WR-pin, the data in the input
register is latched into the command register and all drivers are simultaneously switching to the newly requested status. SPI
communication is ended.
In case the SPI master does only support 16-bit communication, then the master must first send 8 clock pulses with dummy DIN data
and ignoring the DOUT data. For the next 8 clock pulses the above description can be applied.
The required timing for serial to peripheral interface is shown in Table 11.
Table 11: Digital Characteristics
Symbol
T_CLK
T_DATA_ready
Description
Min.
Max.
500
2
Unit
kHz
µs
Maximum applied clock frequency on CLK input
Time between falling edge on WR and first bit of data ready on
DOUT output
(driver going from HZ state to output of first diagnostic bit)
First clock edge from falling edge on WR
Set-up time on DIN
T_CLK_first
T_setup(1)
3
20
20
µs
ns
ns
ns
T_hold(1)
Hold time on DIN
T_DATA_next
Time between rising edge on CLK and next bit ready on DOUT (capa
(capacitor tied to the DOUT pin is 30pF max.)
Time between last CLK edge and WR rising edge
Rise and fall time of all applied signals
(maximum loading capacitance is 30pF)
Time between two rising edge on WR
(repetition of the same command)
100
20
T_SPI_END
T_risefall
1
5
µs
ns
T_WR
300
µs
Note: (1) Guaranteed by design
Normal mode verification:
• The command is the set of eight bits loaded via SPI, which drives the eight HS drivers on or off.
• The command is activated with rising edge on WR pin.
Table 12: Digital Characteristics
Symbol
Description
Min.
Max.
Unit
T_command_L_max.(1)
Minimum time between two opposite commands for inductive
loads and maximum HS driver current of 275mA
Minimum time between two opposite commands for resistive
loads and maximum HS driver current of 350mA
The time between the rising edge on the PDB input and 90
percent of VB-1V on all HS driver outputs. (all drivers are
activated, pure resistive load 35mA on all outputs)
1
s
T_command_R(1)
T_PDB_recov
2
ms
ms
1
Note: (1) Guaranteed by design
AMI Semiconductor – Jan. 07, M-20557-002
10
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AMI [ AMI SEMICONDUCTOR ]
