AMIS-720639:
600dpi CIS Sensor Chip
Data Sheet
Figure 4: Supplement Timing Diagram
This supplementary timing diagram, Figure 4, graphically defines the symbols used to describe the timing relationship between the
waveforms at the output of the voltage buffer amplifier. The accompanying Table 7 is shown below.
Cp is the same clock that is shown in Figure 3. As in the Figure 3, it is the reference for defining the video signal pulse times. Vp is the
peak amplitude of the pixel when the image sensor is under light exposure. Vd is the dark level of the pixel when the image sensor has
no light exposure. The reset level is used during the time when image sensor is reset to ground with an external shunting switch, SW.
Refer to any of the simplified block diagrams in Section 7.0. The video line reset is active while Cp is high. The video signal charges the
video line with the falling edge of Cp.
The shape of the video is a typical characteristic that is exhibited when the sensor current charges the video line capacitance. It
continues to rise until it becomes asymptotic to a horizontal line. However, for a clock frequency >2.0MHz, the slope does not reach the
asymptotic condition. Because of this ever-charging slope, the output voltage changes with the clock frequency and its duty cycle.
Hence, there is no optimum point for the video pixel sampling position. Using an edge-triggered sampling A/D with a very narrow
aperture, the users of these CIS devices sample the signal as close to top of the waveform as possible. Although the optimum way is
to adjust the sampling position in the application, the following sampling time given in terms of clock-time ratio will provide a rule-of-
thumb in setting the sampling time. By using the relationship below, the user can place the sampling clock within an acceptable range.
Tsmp
≈
[to x (1.0 – Dty) + Damp]
where Dty is the clock duty cycle defined in Table 6.
Table 7: Supplement Timing Symbol's Definition
Item
Symbol
(1)
Clock pulse period
to
(2)
Video sample time
tsmp
(3)
Amplifier group delay
Damp
Video fall time
tvf
Notes:
(1)
(2)
(3)
Min.
166
107
15
20
Mean
200
120
20
30
Max.
10000
Units
ns
ns
%
ns
to is the clock cycle period with minimum set with 6.0MHz.
tsmp has been previously defined above, with Dty=0.5.
Damp is group delay time associated with the amplifier design in Figure 7, Video Buffer Amplifier, EL2044 by Elantec.
AMI Semiconductor
– May 06, M-20569-001
www.amis.com
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AMI [ AMI SEMICONDUCTOR ]
