AMIS-42700 Dual High-Speed CAN Transceiver
Preliminary Data Sheet
7.0 Functional Description
7.1 Overall Functional Description
The CAN transceiver is specially designed to provide the link between the protocol IC (CAN controller) and two physical bus lines.
Data interchange between those two bus lines is realized via the interface. Bitwise arbitration is extended on both buses. A fault
like short circuit is limited to that bus line where it occurs. Data interchange from the protocol IC to the other bus system and on this
bus system itself can be continued.
The transceiver can also be used for only one bus system. If the connections for the second bus system are simply left open it
serves as a single transceiver for an electronic unit. For correct operation it is necessary to terminate an open bus. If not, the open
bus will disturb the other one, e.g. in case of open load.
The bus lines can have two logical states, dominant or recessive. A bus is in the recessive state when the driving sections of all
transceivers connected to the bus are passive. The differential voltage between the two wires is approximately zero. If at least one
driver is active the bus changes into the dominant state. This state is represented by a differential voltage greater than a minimum
threshold and therefore by a current flow through the terminating resistors of the bus line. The recessive state is overwritten by the
dominant state.
To provide an independent switch-off of the transceiver units for both bus systems by a third device (e.g. the µC) enables inputs for
the corresponding driving and receiving sections to be included.
7.2 Transmitter
The transceiver includes two transmitters, one for each bus line and a driver control circuit. Each transmitter is implemented as a
push and a pull driver. The drivers will be active if the transmission of a dominant bit is required. During the transmission of a
recessive bit all drivers are passive. The transmitters have a built-in current limiting circuit that protects the driver stages from
damage caused by accidental short circuit to either positive supply voltage or to ground. Additionally a thermal protection circuit is
integrated.
The driver control circuit ensures that the drivers are switched on and off with a controlled slope to limit EME. The driver control
circuit will be controlled itself by the thermal protection circuit, the timer circuit, the ENBx inputs, and the logic unit.
The dominant time out timer circuit prevents the output drivers from driving a permanent dominant state (blocking all network
communication) if pin Tx0 or the bus lines of the other bus are forced permanently dominant by a hardware and/or software failure
(see tdom(TxD)).
The enable signal ENBx allows the transmitter to be switched off by a third device (e.g. the µC). In the disabled state (ENBx =
high) the corresponding transmitter behaves as in the recessive state and does not depend on the input voltage at Tx0 nor on the
state of the other bus system.
7.3 Receiver
Two bus receiving sections sense the states of the bus lines. Each receiver section consists of an input filter and a fast and
accurate comparator. The aim of the input filter is to improve the immunity against high-frequency disturbances and also to
convert the voltage at the bus lines CANHx and CANLx, which can vary from –12V to +12V, to voltages in the range 0 to 5V, which
can be applied to the comparators.
The output signal of the comparators is gated by the ENBx signal. In the disabled state (ENBX = high) the output signal of the
comparator will be replaced by a permanently recessive state and does not depend on the bus voltage. In the enabled state the
receiver signal sent to the logic unit is identical to the comparator output signal.
AMI Semiconductor
– Rev. 1.4, May 05 - Preliminary
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