AMIS-30623 LIN Microstepping Motordriver
Data Sheet
The <StepLoss> signal is used to block successive motions. Also this signal will be cleared after Vbb > UV1, making updates of
TagPospossible.
The implementation is illustrated in the state diagram below.
HS = f (UV2SIG, OVC1, OVC2, CPFail, …)
If UV2SIG = 1 THEN TagPos ≠ ActPos
ELSE copy TagPos = ActPos
GotoPos
ShutDown
HardStop
Stopped
GetStatus
GetFullStatus
PWM disabled
Motor in HiZ
HS to Positioner
Vbb > UV1
TagPos ≠ ActPos
Figure 18: State Diagram Autarkic Under-voltage Handling
In Stop mode 1 AMIS-30623 is in the Stopped state. Because Vbb < UV2 it enters the ShutDown state. Once Vbb > UV1 the Stopped
state will be entered again.
In Stop mode 2 AMIS-30623 is in the GotoPos state. Because Vbb < UV2 the UV2SIG is set and the HardStop state is entered. After
the hardstop motion is finished (HS to Positioner) it enters the Stopped state. UV2SIG = 1 so the TagPos is not copied in Actpos, and
the shutdown stated is entered. Once Vbb > UV1 the Stopped state will be entered again and because TagPos = Actpos C623 moves
to GotoPos again. <UV2SIG>, <CPFail> and <Steploss> are cleared when Vbb > UV1 so HardStop is not entered again.
15.2.8. OTP register
OTP Memory Structure
The table below shows how the parameters to be stored in the OTP memory are located.
Table 17: OTP Memory Structure
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Bit 7
OSC3
EnableLIN
AbsThr3
Irun3
Bit 6
OSC2
TSD2
AbsThr2
Irun2
Vmax2
SecPos9
SecPos6
DelThr2
Bit 5
OSC1
TSD1
AbsThr1
Irun1
Vmax1
SecPos8
SecPos5
DelThr1
Bit 4
OSC0
TSD0
AbsThr0
Irun0
Vmax0
Shaft
SecPos4
DelThr0
Bit 3
IREF3
BG3
Bit 2
IREF2
BG2
Bit 1
IREF1
BG1
Bit 0
IREF0
BG0
PA3
PA2
PA1
PA0
Ihold3
Vmin3
Acc3
SecPos3
StepMode1
Ihold2
Vmin2
Acc2
SecPos2
StepMode0
Ihold1
Vmin1
Acc1
Failsafe
LOCKBT
Ihold0
Vmin0
Acc0
SleepEn
LOCKBG
Vmax3
SecPos10
SecPos7
DelThr3
Parameters stored at address 0x00 and 0x01 and bit LOCKBT are already programmed in the OTP memory at circuit delivery. They
correspond to the calibration of the circuit and are just documented here as an indication.
Each OPT bit is at ‘0’ when not zapped. Zapping a bit will set it to ‘1’. Thus only bits having to be at ‘1’ must be zapped. Zapping of a bit
already at ‘1’ is disabled. Each OTP byte will be programmed separately (see command SetOTPparam). Once OTP programming is
completed, bit LOCKBG can be zapped, to disable future zapping, otherwise any OTP bit at ‘0’ could still be zapped by using a
SetOTPparamcommand.
AMI Semiconductor – June 2006, Rev 3.0
26
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